Hardware enhanced run-time management for many-core processors:
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
Düren
Shaker Verlag
2019
|
| Series: | Berichte aus der Elektrotechnik
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | iii, 179 Seiten Illustrationen, Diagramme 21 cm x 14.8 cm, 269 g |
| ISBN: | 9783844066234 3844066233 |
Staff View
MARC
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| 100 | 1 | |a Gregorek, Daniel |e Verfasser |0 (DE-588)1186721537 |4 aut | |
| 245 | 1 | 0 | |a Hardware enhanced run-time management for many-core processors |c Daniel Gregorek |
| 264 | 1 | |a Düren |b Shaker Verlag |c 2019 | |
| 300 | |a iii, 179 Seiten |b Illustrationen, Diagramme |c 21 cm x 14.8 cm, 269 g | ||
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| 490 | 0 | |a Berichte aus der Elektrotechnik | |
| 502 | |b Dissertation |c Universität Bremen |d 2018 | ||
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| 653 | |a Many-Core Processors | ||
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Record in the Search Index
| _version_ | 1804180085473804288 |
|---|---|
| adam_text | CONTENTS
1
INTRODUCTION
1
1.1
PROBLEM
DESCRIPTION
...................................................................................
1
1.2
CONTRIBUTION
...............................................................................................
2
1.3
ORGANIZATION
...............................................................................................
4
2
FUNDAMENTALS
5
2.1
MANY-CORE
COMPUTING
................................................................................
5
2.1.1
NANOMETER-CMOS
.........................................................................
6
2.1.2
MANY-CORE
ARCHITECTURE
................................................................
8
2.1.3
DARK
SILICON
......................................................................................
11
2.1.4
APPLICATIONS
AND
CONCURRENCY
....................................................
12
2.2
RUN-TIME
MANAGEMENT
............................................................................
13
2.2.1
FUNDAMENTAL
CONCEPTS
...................................................................
14
2.2.2
SYNCHRONIZATION
AND
COMMUNICATION
...........................................
15
2.2.3
SCHEDULING
AND
MAPPING
................................................................
17
2.2.4
POWER
MANAGEMENT
......................................................................
20
2.2.5
RTM
CLASSIFICATION
.........................................................................
22
2.2.6
MANY-CORE
RTM
............................................................................
23
2.3
HARDWARE
ENHANCED
RTM
.........................................................................
26
2.3.1
HARDWARE
ARCHITECTURE
...................................................................
28
2.3.2
ENHANCEMENTS
FOR
SYNCHRONIZATION
..............................................
29
2.3.3
ENHANCEMENTS
FOR
SCHEDULING
.......................................................
32
2.4
SUMMARY
.....................................................................................................
36
3
DRACON
ARCHITECTURE
37
3.1
INTRODUCTION
..................................................................................................
37
3.2
RELATED
WORK
.............................................
39
3.3
RTM
ARCHITECTURE
......................................................................................
40
3.3.1
RTM
TAXONOMY
............................................................................
40
3.3.2
ANALYTICAL
TIMING
MODEL
..............................................................
41
3.4
HARDWARE
ARCHITECTURE
................................................................................
43
3.4.1
BASELINE
SYSTEM
.............................................................................
44
I
CONTENTS
3.4.2
DEDICATED
INFRASTRUCTURE
.................................................................
45
3.5
TASK
MANAGEMENT
......................................................................................
47
3.5.1
TASK
MAPPING
AND
SCHEDULING
....................................................
49
3.5.2
TASK
SYNCHRONIZATION
AND
COMMUNICATION
..................................
49
3.5.3
APPLICATION
START-UP
.......................................................................
51
3.5.4
LOAD
BALANCING
................................................................................
52
3.5.5
DEDICATED
MESSAGE
PROTOCOL
...........................................................
52
3.6
RT-LEVEL
IMPLEMENTATION
..........................................................................
54
3.7
GATE-LEVEL
ANALYSIS
...................................................................................
57
3.8
SUMMARY
......................................................................................................
58
4
AGAMID
FRAMEWORK
61
4.1
MANY-CORE
SIMULATION
................................................................................
62
4.1.1
SIMULATION
SCOPE
.............................................................................
63
4.1.2
SIMULATION
SPEED
.............................................................................
64
4.2
RELATED
WORK
...............................................................................................
66
4.3
AGAMID
APPROACH
......................................................................................
68
4.4
IMPLEMENTATION
............................................................................................
69
4.4.1
PROCESSING
CORE
.............................................................................
70
4.4.2
HARDWARE
ENHANCED
RTM
..............................................................
72
4.4.3
INTERCONNECT
...................................................................................
75
4.5
GENERIC
RUN-TIME
MANAGER
.......................................................................
78
4.5.1
GENERIC
RTM
MASTER
....................................................................
79
4.5.2
GENERIC
TASK
MANAGER
....................................................................
79
4.6
TASK
DESCRIPTION
LANGUAGE
.......................................................................
82
4.7
TASK
EXECUTION
MODEL
................................................................................
83
4.8
CALIBRATION
..................................................................................................
83
4.8.1
BASELINE
SYSTEM
.............................................................................
85
4.8.2
HARDWARE
ACCELERATORS
....................................................................
87
4.9
SUMMARY
......................................................................................................
91
5
EVALUATION
93
5.1
EXPERIMENTAL
SETUP
...................................................................................
93
5.2
SYNTHETIC
BENCHMARKS
................................................................................
95
5.2.1
SCHEDULING
......................................................................................
95
5.2.2
TASK
MAPPING
................................................................................
99
5.2.3
SYNCHRONIZATION
................................................................................
104
5.2.4
DISPATCHING
.........................................................................................
107
5.2.5
ONLINE
LOAD
BALANCING
.......................................................................
109
II
CONTENTS
5.2.6
RTM
MASTER
......................................................................................
109
5.2.7
SENSITIVITY
TO
INTERCONNECTS
.............................................................
ILL
5.3
MCSL
BENCHMARKS
.........................................................................................
115
5.3.1
SINGLE-PROGRAM
...................................................................................
115
5.3.2
MULTI-PROGRAM
...................................................................................
118
5.3.3
RANDOM
INJECTION
.............................................................................
124
5.4
EVALUATION
OF
AGAMID
...................................................................................
128
5.4.1
SIMULATION
SPEED
................................................................................
129
5.4.2
SIMULATION
ACCURACY
..........................................................................
130
6
CONCLUSIONS
133
6.1
CONTRIBUTIONS
..................................................................................................
133
6.2
OUTLOOK
...........................................................................................................
135
A
APPENDIX
137
A.L
DRAGON
.......................................................................................................
137
A.
1.1
DRAGON
SYSTEM
CALLS
..................................................................
137
A.
1.2
DRAGON
MESSAGES
........................................................................
138
A.
1.3
DRAGON
C-LIBRARY
........................................................................
139
A.
2
AGAMID
...........................................................................................................
141
A.
2.1
AGAMID
GENERIC
RTM
TEMPLATES
....................................................
141
A.
2.2
AGAMID
MANUAL
................................................................................
144
A.
3
MCSL
BENCHMARK
........................................................................................
145
A.
3.1
MCSL
TASK
GRAPHS
..........................................................................
145
A.
3.2
OFFLINE
GRAPH
CLUSTERING
...................................................................
147
A.
3.3
SINGLE-PROGRAM
...................................................................................
150
A.
3.4
MULTI-PROGRAM
...................................................................................
154
III
|
| any_adam_object | 1 |
| author | Gregorek, Daniel |
| author_GND | (DE-588)1186721537 |
| author_facet | Gregorek, Daniel |
| author_role | aut |
| author_sort | Gregorek, Daniel |
| author_variant | d g dg |
| building | Verbundindex |
| bvnumber | BV045912785 |
| classification_rvk | ZN 4940 |
| ctrlnum | (OCoLC)1100546837 (DE-599)DNB1180061527 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Thesis Book |
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| illustrated | Illustrated |
| indexdate | 2024-07-10T08:30:09Z |
| institution | BVB |
| institution_GND | (DE-588)1064118135 |
| isbn | 9783844066234 3844066233 |
| language | English |
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| owner | DE-83 DE-634 |
| owner_facet | DE-83 DE-634 |
| physical | iii, 179 Seiten Illustrationen, Diagramme 21 cm x 14.8 cm, 269 g |
| publishDate | 2019 |
| publishDateSearch | 2019 |
| publishDateSort | 2019 |
| publisher | Shaker Verlag |
| record_format | marc |
| series2 | Berichte aus der Elektrotechnik |
| spelling | Gregorek, Daniel Verfasser (DE-588)1186721537 aut Hardware enhanced run-time management for many-core processors Daniel Gregorek Düren Shaker Verlag 2019 iii, 179 Seiten Illustrationen, Diagramme 21 cm x 14.8 cm, 269 g txt rdacontent n rdamedia nc rdacarrier Berichte aus der Elektrotechnik Dissertation Universität Bremen 2018 SystemC (DE-588)4737678-8 gnd rswk-swf Hardwareerweiterung (DE-588)4159104-5 gnd rswk-swf Mehrkernprozessor (DE-588)7598578-0 gnd rswk-swf Leistungsbewertung (DE-588)4167271-9 gnd rswk-swf Laufzeit (DE-588)4166917-4 gnd rswk-swf MIMD (DE-588)4300178-6 gnd rswk-swf Transaktionsebenenmodellierung (DE-588)1047571560 gnd rswk-swf Betriebsmittelverwaltung (DE-588)4417917-0 gnd rswk-swf Architektur Informatik (DE-588)4139374-0 gnd rswk-swf Register-Transfer-Ebene (DE-588)4215789-4 gnd rswk-swf Hardware Many-Core Processors Rechnerarchitektur (DE-588)4113937-9 Hochschulschrift gnd-content Mehrkernprozessor (DE-588)7598578-0 s Betriebsmittelverwaltung (DE-588)4417917-0 s Hardwareerweiterung (DE-588)4159104-5 s MIMD (DE-588)4300178-6 s SystemC (DE-588)4737678-8 s Transaktionsebenenmodellierung (DE-588)1047571560 s Register-Transfer-Ebene (DE-588)4215789-4 s Architektur Informatik (DE-588)4139374-0 s Laufzeit (DE-588)4166917-4 s Leistungsbewertung (DE-588)4167271-9 s DE-604 Shaker Verlag (DE-588)1064118135 pbl DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031295324&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Gregorek, Daniel Hardware enhanced run-time management for many-core processors SystemC (DE-588)4737678-8 gnd Hardwareerweiterung (DE-588)4159104-5 gnd Mehrkernprozessor (DE-588)7598578-0 gnd Leistungsbewertung (DE-588)4167271-9 gnd Laufzeit (DE-588)4166917-4 gnd MIMD (DE-588)4300178-6 gnd Transaktionsebenenmodellierung (DE-588)1047571560 gnd Betriebsmittelverwaltung (DE-588)4417917-0 gnd Architektur Informatik (DE-588)4139374-0 gnd Register-Transfer-Ebene (DE-588)4215789-4 gnd |
| subject_GND | (DE-588)4737678-8 (DE-588)4159104-5 (DE-588)7598578-0 (DE-588)4167271-9 (DE-588)4166917-4 (DE-588)4300178-6 (DE-588)1047571560 (DE-588)4417917-0 (DE-588)4139374-0 (DE-588)4215789-4 (DE-588)4113937-9 |
| title | Hardware enhanced run-time management for many-core processors |
| title_auth | Hardware enhanced run-time management for many-core processors |
| title_exact_search | Hardware enhanced run-time management for many-core processors |
| title_full | Hardware enhanced run-time management for many-core processors Daniel Gregorek |
| title_fullStr | Hardware enhanced run-time management for many-core processors Daniel Gregorek |
| title_full_unstemmed | Hardware enhanced run-time management for many-core processors Daniel Gregorek |
| title_short | Hardware enhanced run-time management for many-core processors |
| title_sort | hardware enhanced run time management for many core processors |
| topic | SystemC (DE-588)4737678-8 gnd Hardwareerweiterung (DE-588)4159104-5 gnd Mehrkernprozessor (DE-588)7598578-0 gnd Leistungsbewertung (DE-588)4167271-9 gnd Laufzeit (DE-588)4166917-4 gnd MIMD (DE-588)4300178-6 gnd Transaktionsebenenmodellierung (DE-588)1047571560 gnd Betriebsmittelverwaltung (DE-588)4417917-0 gnd Architektur Informatik (DE-588)4139374-0 gnd Register-Transfer-Ebene (DE-588)4215789-4 gnd |
| topic_facet | SystemC Hardwareerweiterung Mehrkernprozessor Leistungsbewertung Laufzeit MIMD Transaktionsebenenmodellierung Betriebsmittelverwaltung Architektur Informatik Register-Transfer-Ebene Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=031295324&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT gregorekdaniel hardwareenhancedruntimemanagementformanycoreprocessors AT shakerverlag hardwareenhancedruntimemanagementformanycoreprocessors |