Skew-tolerant circuit design:
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
San Francisco
Morgan Kaufmann Publishers
2001
|
| Series: | Morgan Kaufmann series in computer architecture and design
|
| Subjects: | |
| Item Description: | Print version record |
| Physical Description: | 1 online resource (xiv, 223 pages) illustrations |
| ISBN: | 9780080541266 0080541267 9781558606364 155860636X 1281078042 9781281078049 |
Staff View
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045343886 | ||
| 003 | DE-604 | ||
| 005 | 20200210 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 181206s2001 |||| o||u| ||||||eng d | ||
| 020 | |a 9780080541266 |9 978-0-08-054126-6 | ||
| 020 | |a 0080541267 |9 0-08-054126-7 | ||
| 020 | |a 9781558606364 |9 978-1-55860-636-4 | ||
| 020 | |a 155860636X |9 1-55860-636-X | ||
| 020 | |a 1281078042 |9 1-281-07804-2 | ||
| 020 | |a 9781281078049 |9 978-1-281-07804-9 | ||
| 035 | |a (ZDB-4-ENC)ocn647697026 | ||
| 035 | |a (OCoLC)647697026 | ||
| 035 | |a (DE-599)BVBBV045343886 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.3815 |2 21 | |
| 100 | 1 | |a Harris, David Money |d 19XX- |e Verfasser |0 (DE-588)173938035 |4 aut | |
| 245 | 1 | 0 | |a Skew-tolerant circuit design |c David Harris |
| 264 | 1 | |a San Francisco |b Morgan Kaufmann Publishers |c 2001 | |
| 300 | |a 1 online resource (xiv, 223 pages) |b illustrations | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Morgan Kaufmann series in computer architecture and design | |
| 500 | |a Print version record | ||
| 505 | 8 | |a As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / General |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Design and construction |2 fast | |
| 650 | 7 | |a Synchronization |2 fast | |
| 650 | 7 | |a Timing circuits / Design and construction |2 fast | |
| 650 | 4 | |a Timing circuits |x Design and construction |a Integrated circuits |x Very large scale integration |x Design and construction |a Synchronization | |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |a Harris, David (David Lewis) |t Skew-tolerant circuit design |d San Francisco : Morgan Kaufmann Publishers, 2001 |
| 912 | |a ZDB-4-ENC | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030730590 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Record in the Search Index
| _version_ | 1804179163055128576 |
|---|---|
| any_adam_object | |
| author | Harris, David Money 19XX- |
| author_GND | (DE-588)173938035 |
| author_facet | Harris, David Money 19XX- |
| author_role | aut |
| author_sort | Harris, David Money 19XX- |
| author_variant | d m h dm dmh |
| building | Verbundindex |
| bvnumber | BV045343886 |
| collection | ZDB-4-ENC |
| contents | As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises |
| ctrlnum | (ZDB-4-ENC)ocn647697026 (OCoLC)647697026 (DE-599)BVBBV045343886 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03509nmm a2200505zc 4500</leader><controlfield tag="001">BV045343886</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20200210 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">181206s2001 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080541266</subfield><subfield code="9">978-0-08-054126-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080541267</subfield><subfield code="9">0-08-054126-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781558606364</subfield><subfield code="9">978-1-55860-636-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">155860636X</subfield><subfield code="9">1-55860-636-X</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1281078042</subfield><subfield code="9">1-281-07804-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781281078049</subfield><subfield code="9">978-1-281-07804-9</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-4-ENC)ocn647697026</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)647697026</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045343886</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">21</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Harris, David Money</subfield><subfield code="d">19XX-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)173938035</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Skew-tolerant circuit design</subfield><subfield code="c">David Harris</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">San Francisco</subfield><subfield code="b">Morgan Kaufmann Publishers</subfield><subfield code="c">2001</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xiv, 223 pages)</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Morgan Kaufmann series in computer architecture and design</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Print version record</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / General</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Synchronization</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Timing circuits / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Timing circuits</subfield><subfield code="x">Design and construction</subfield><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield><subfield code="a">Synchronization</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="a">Harris, David (David Lewis)</subfield><subfield code="t">Skew-tolerant circuit design</subfield><subfield code="d">San Francisco : Morgan Kaufmann Publishers, 2001</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-ENC</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030730590</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV045343886 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:15:29Z |
| institution | BVB |
| isbn | 9780080541266 0080541267 9781558606364 155860636X 1281078042 9781281078049 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030730590 |
| oclc_num | 647697026 |
| open_access_boolean | |
| physical | 1 online resource (xiv, 223 pages) illustrations |
| psigel | ZDB-4-ENC |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| series2 | Morgan Kaufmann series in computer architecture and design |
| spelling | Harris, David Money 19XX- Verfasser (DE-588)173938035 aut Skew-tolerant circuit design David Harris San Francisco Morgan Kaufmann Publishers 2001 1 online resource (xiv, 223 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in computer architecture and design Print version record As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Integrated circuits / Very large scale integration / Design and construction fast Synchronization fast Timing circuits / Design and construction fast Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 Erscheint auch als Druck-Ausgabe Harris, David (David Lewis) Skew-tolerant circuit design San Francisco : Morgan Kaufmann Publishers, 2001 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Harris, David Money 19XX- Skew-tolerant circuit design As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Integrated circuits / Very large scale integration / Design and construction fast Synchronization fast Timing circuits / Design and construction fast Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4027242-4 |
| title | Skew-tolerant circuit design |
| title_auth | Skew-tolerant circuit design |
| title_exact_search | Skew-tolerant circuit design |
| title_full | Skew-tolerant circuit design David Harris |
| title_fullStr | Skew-tolerant circuit design David Harris |
| title_full_unstemmed | Skew-tolerant circuit design David Harris |
| title_short | Skew-tolerant circuit design |
| title_sort | skew tolerant circuit design |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Integrated circuits / Very large scale integration / Design and construction fast Synchronization fast Timing circuits / Design and construction fast Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated TECHNOLOGY & ENGINEERING / Electronics / Circuits / General Integrated circuits / Very large scale integration / Design and construction Synchronization Timing circuits / Design and construction Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung |
| work_keys_str_mv | AT harrisdavidmoney skewtolerantcircuitdesign |