Metamodeling-driven IP reuse for SoC integration and microprocessor design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Artech House
2009
|
| Schlagworte: | |
| Beschreibung: | Print version record |
| Beschreibung: | 1 online resource (xxi, 287 pages) illustrations |
| ISBN: | 9781596934252 1596934255 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV045343400 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 181206s2009 |||| o||u| ||||||eng d | ||
| 020 | |a 9781596934252 |9 978-1-59693-425-2 | ||
| 020 | |a 1596934255 |9 1-59693-425-5 | ||
| 035 | |a (ZDB-4-ENC)ocn547448110 | ||
| 035 | |a (OCoLC)547448110 | ||
| 035 | |a (DE-599)BVBBV045343400 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.39/5 |2 22 | |
| 100 | 1 | |a Mathaikutty, Deepak A. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Metamodeling-driven IP reuse for SoC integration and microprocessor design |c Deepak A. Mathaikutty, Sandeep K. Shukla |
| 264 | 1 | |a Boston |b Artech House |c 2009 | |
| 300 | |a 1 online resource (xxi, 287 pages) |b illustrations | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Print version record | ||
| 505 | 8 | |a This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The book covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a (3z (Bwrite once, use many times (3y (Bverification strategy – another effective approach that can attain a faster product design cycle | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic |2 bisacsh | |
| 650 | 7 | |a COMPUTERS / Logic Design |2 bisacsh | |
| 650 | 7 | |a Computer software / Reusability |2 fast | |
| 650 | 7 | |a Computer software / Verification |2 fast | |
| 650 | 7 | |a Intellectual property |2 fast | |
| 650 | 7 | |a Microprocessors / Design and construction |2 fast | |
| 650 | 7 | |a System design |2 fast | |
| 650 | 7 | |a Systems on a chip / Design and construction |2 fast | |
| 650 | 4 | |a Computer software |x Reusability |a Computer software |x Verification |a Systems on a chip |x Design and construction |a Microprocessors |x Design and construction |a Intellectual property |a System design | |
| 700 | 1 | |a Shukla, Sandeep K. |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |a Mathaikutty, Deepak A. |t Metamodeling-driven IP reuse for SoC integration and microprocessor design |d Boston : Artech House, 2009 |z 9781596934245 |
| 912 | |a ZDB-4-ENC | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030730102 | ||
Datensatz im Suchindex
| _version_ | 1804179162129235968 |
|---|---|
| any_adam_object | |
| author | Mathaikutty, Deepak A. |
| author_facet | Mathaikutty, Deepak A. |
| author_role | aut |
| author_sort | Mathaikutty, Deepak A. |
| author_variant | d a m da dam |
| building | Verbundindex |
| bvnumber | BV045343400 |
| collection | ZDB-4-ENC |
| contents | This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The book covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a (3z (Bwrite once, use many times (3y (Bverification strategy – another effective approach that can attain a faster product design cycle |
| ctrlnum | (ZDB-4-ENC)ocn547448110 (OCoLC)547448110 (DE-599)BVBBV045343400 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02586nmm a2200457zc 4500</leader><controlfield tag="001">BV045343400</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">181206s2009 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781596934252</subfield><subfield code="9">978-1-59693-425-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1596934255</subfield><subfield code="9">1-59693-425-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-4-ENC)ocn547448110</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)547448110</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045343400</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Mathaikutty, Deepak A.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Metamodeling-driven IP reuse for SoC integration and microprocessor design</subfield><subfield code="c">Deepak A. Mathaikutty, Sandeep K. Shukla</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston</subfield><subfield code="b">Artech House</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xxi, 287 pages)</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Print version record</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The book covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a (3z (Bwrite once, use many times (3y (Bverification strategy – another effective approach that can attain a faster product design cycle</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS / Logic Design</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer software / Reusability</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer software / Verification</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Intellectual property</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Microprocessors / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">System design</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Systems on a chip / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer software</subfield><subfield code="x">Reusability</subfield><subfield code="a">Computer software</subfield><subfield code="x">Verification</subfield><subfield code="a">Systems on a chip</subfield><subfield code="x">Design and construction</subfield><subfield code="a">Microprocessors</subfield><subfield code="x">Design and construction</subfield><subfield code="a">Intellectual property</subfield><subfield code="a">System design</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Shukla, Sandeep K.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="a">Mathaikutty, Deepak A.</subfield><subfield code="t">Metamodeling-driven IP reuse for SoC integration and microprocessor design</subfield><subfield code="d">Boston : Artech House, 2009</subfield><subfield code="z">9781596934245</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-ENC</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030730102</subfield></datafield></record></collection> |
| id | DE-604.BV045343400 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:15:29Z |
| institution | BVB |
| isbn | 9781596934252 1596934255 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030730102 |
| oclc_num | 547448110 |
| open_access_boolean | |
| physical | 1 online resource (xxi, 287 pages) illustrations |
| psigel | ZDB-4-ENC |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Artech House |
| record_format | marc |
| spelling | Mathaikutty, Deepak A. Verfasser aut Metamodeling-driven IP reuse for SoC integration and microprocessor design Deepak A. Mathaikutty, Sandeep K. Shukla Boston Artech House 2009 1 online resource (xxi, 287 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Print version record This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The book covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a (3z (Bwrite once, use many times (3y (Bverification strategy – another effective approach that can attain a faster product design cycle TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Computer software / Reusability fast Computer software / Verification fast Intellectual property fast Microprocessors / Design and construction fast System design fast Systems on a chip / Design and construction fast Computer software Reusability Computer software Verification Systems on a chip Design and construction Microprocessors Design and construction Intellectual property System design Shukla, Sandeep K. Sonstige oth Erscheint auch als Druck-Ausgabe Mathaikutty, Deepak A. Metamodeling-driven IP reuse for SoC integration and microprocessor design Boston : Artech House, 2009 9781596934245 |
| spellingShingle | Mathaikutty, Deepak A. Metamodeling-driven IP reuse for SoC integration and microprocessor design This cutting-edge resource offers you an in-depth understanding of metamodeling approaches for the reuse of intellectual properties (IPs) in the form of reusable design or verification components. The book covers the essential issues associated with fast and effective integration of reusable design components into a system-on-a-chip (SoC) to achieve faster design turn-around time. Moreover, it addresses key factors related to the use of reusable verification IPs for a (3z (Bwrite once, use many times (3y (Bverification strategy – another effective approach that can attain a faster product design cycle TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Computer software / Reusability fast Computer software / Verification fast Intellectual property fast Microprocessors / Design and construction fast System design fast Systems on a chip / Design and construction fast Computer software Reusability Computer software Verification Systems on a chip Design and construction Microprocessors Design and construction Intellectual property System design |
| title | Metamodeling-driven IP reuse for SoC integration and microprocessor design |
| title_auth | Metamodeling-driven IP reuse for SoC integration and microprocessor design |
| title_exact_search | Metamodeling-driven IP reuse for SoC integration and microprocessor design |
| title_full | Metamodeling-driven IP reuse for SoC integration and microprocessor design Deepak A. Mathaikutty, Sandeep K. Shukla |
| title_fullStr | Metamodeling-driven IP reuse for SoC integration and microprocessor design Deepak A. Mathaikutty, Sandeep K. Shukla |
| title_full_unstemmed | Metamodeling-driven IP reuse for SoC integration and microprocessor design Deepak A. Mathaikutty, Sandeep K. Shukla |
| title_short | Metamodeling-driven IP reuse for SoC integration and microprocessor design |
| title_sort | metamodeling driven ip reuse for soc integration and microprocessor design |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Computer software / Reusability fast Computer software / Verification fast Intellectual property fast Microprocessors / Design and construction fast System design fast Systems on a chip / Design and construction fast Computer software Reusability Computer software Verification Systems on a chip Design and construction Microprocessors Design and construction Intellectual property System design |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Computer software / Reusability Computer software / Verification Intellectual property Microprocessors / Design and construction System design Systems on a chip / Design and construction Computer software Reusability Computer software Verification Systems on a chip Design and construction Microprocessors Design and construction Intellectual property System design |
| work_keys_str_mv | AT mathaikuttydeepaka metamodelingdrivenipreuseforsocintegrationandmicroprocessordesign AT shuklasandeepk metamodelingdrivenipreuseforsocintegrationandmicroprocessordesign |