System-on-chip test architectures: nanometer design for testability
Saved in:
| Format: | Electronic eBook |
|---|---|
| Language: | English |
| Published: |
Amsterdam ; Boston
Morgan Kaufmann Publishers
2008
|
| Series: | Morgan Kaufmann series in systems on silicon
|
| Subjects: | |
| Item Description: | Print version record |
| Physical Description: | 1 online resource (xxxvi, 856 pages) illustrations |
| ISBN: | 9780123739735 012373973X 9780080556802 0080556809 |
Staff View
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| 505 | 8 | |a Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students | |
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| contents | Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students |
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| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
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| dewey-search | 621.39/5 |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| spelling | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba Amsterdam ; Boston Morgan Kaufmann Publishers 2008 1 online resource (xxxvi, 856 pages) illustrations txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Print version record Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast VLSI gnd Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content VLSI (DE-588)4117388-0 s 1\p DE-604 Wang, Laung-Terng Sonstige oth Stroud, Charles E. Sonstige oth Touba, Nur A. Sonstige oth Erscheint auch als Druck-Ausgabe System-on-chip test architectures Amsterdam ; Boston : Morgan Kaufmann Publishers, 2008 9780123739735 012373973X 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | System-on-chip test architectures nanometer design for testability Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast VLSI gnd Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4173536-5 |
| title | System-on-chip test architectures nanometer design for testability |
| title_auth | System-on-chip test architectures nanometer design for testability |
| title_exact_search | System-on-chip test architectures nanometer design for testability |
| title_full | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| title_fullStr | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| title_full_unstemmed | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| title_short | System-on-chip test architectures |
| title_sort | system on chip test architectures nanometer design for testability |
| title_sub | nanometer design for testability |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast VLSI gnd Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Systems on a chip / Testing Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design VLSI Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Patentschrift |
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