Digital system design with FPGA: implementation using Verilog and VHDL
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
New York, NY
McGraw-Hill Education
[2017]
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturverzeichnis Seite 369-371 |
| Physical Description: | xv, 384 Seiten Illustrationen, Diagramme 25 cm |
| ISBN: | 1259837904 9781259837906 |
Staff View
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV045198373 | ||
| 003 | DE-604 | ||
| 005 | 20220617 | ||
| 007 | t | ||
| 008 | 180918s2017 a||| |||| 00||| eng d | ||
| 020 | |a 1259837904 |9 1-259-83790-4 | ||
| 020 | |a 9781259837906 |9 978-1-259-83790-6 | ||
| 035 | |a (OCoLC)1053839965 | ||
| 035 | |a (DE-599)HEB418930902 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-573 |a DE-739 | ||
| 050 | 0 | |a TK7895.G36 | |
| 084 | |a ZN 5400 |0 (DE-625)157454: |2 rvk | ||
| 084 | |a ZN 5430 |0 (DE-625)157458: |2 rvk | ||
| 084 | |a ZN 5600 |0 (DE-625)157468: |2 rvk | ||
| 084 | |a ZN 5630 |0 (DE-625)157471: |2 rvk | ||
| 100 | 1 | |a Ünsalan, Cem |d 1973- |e Verfasser |0 (DE-588)1253535868 |4 aut | |
| 245 | 1 | 0 | |a Digital system design with FPGA |b implementation using Verilog and VHDL |c Cem Ünsalan, Bora Tar |
| 264 | 1 | |a New York, NY |b McGraw-Hill Education |c [2017] | |
| 300 | |a xv, 384 Seiten |b Illustrationen, Diagramme |c 25 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Literaturverzeichnis Seite 369-371 | ||
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 1 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Tar, Bora |d ca. 20./21. Jh. |e Verfasser |0 (DE-588)1260088367 |4 aut | |
| 856 | 4 | 2 | |m V:DE-603;B:DE-17 |q application/pdf |u http://scans.hebis.de/HEBCGI/show.pl?41893090_toc.pdf |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030587401 | ||
Record in the Search Index
| _version_ | 1804178900817805312 |
|---|---|
| any_adam_object | |
| author | Ünsalan, Cem 1973- Tar, Bora ca. 20./21. Jh |
| author_GND | (DE-588)1253535868 (DE-588)1260088367 |
| author_facet | Ünsalan, Cem 1973- Tar, Bora ca. 20./21. Jh |
| author_role | aut aut |
| author_sort | Ünsalan, Cem 1973- |
| author_variant | c ü cü b t bt |
| building | Verbundindex |
| bvnumber | BV045198373 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.G36 |
| callnumber-search | TK7895.G36 |
| callnumber-sort | TK 47895 G36 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 5400 ZN 5430 ZN 5600 ZN 5630 |
| ctrlnum | (OCoLC)1053839965 (DE-599)HEB418930902 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01703nam a2200445 c 4500</leader><controlfield tag="001">BV045198373</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20220617 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">180918s2017 a||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1259837904</subfield><subfield code="9">1-259-83790-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781259837906</subfield><subfield code="9">978-1-259-83790-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1053839965</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)HEB418930902</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-739</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7895.G36</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5400</subfield><subfield code="0">(DE-625)157454:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5430</subfield><subfield code="0">(DE-625)157458:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5600</subfield><subfield code="0">(DE-625)157468:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5630</subfield><subfield code="0">(DE-625)157471:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ünsalan, Cem</subfield><subfield code="d">1973-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1253535868</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital system design with FPGA</subfield><subfield code="b">implementation using Verilog and VHDL</subfield><subfield code="c">Cem Ünsalan, Bora Tar</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York, NY</subfield><subfield code="b">McGraw-Hill Education</subfield><subfield code="c">[2017]</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xv, 384 Seiten</subfield><subfield code="b">Illustrationen, Diagramme</subfield><subfield code="c">25 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Literaturverzeichnis Seite 369-371</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Tar, Bora</subfield><subfield code="d">ca. 20./21. Jh.</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)1260088367</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">V:DE-603;B:DE-17</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://scans.hebis.de/HEBCGI/show.pl?41893090_toc.pdf</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030587401</subfield></datafield></record></collection> |
| id | DE-604.BV045198373 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T08:11:19Z |
| institution | BVB |
| isbn | 1259837904 9781259837906 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030587401 |
| oclc_num | 1053839965 |
| open_access_boolean | |
| owner | DE-573 DE-739 |
| owner_facet | DE-573 DE-739 |
| physical | xv, 384 Seiten Illustrationen, Diagramme 25 cm |
| publishDate | 2017 |
| publishDateSearch | 2017 |
| publishDateSort | 2017 |
| publisher | McGraw-Hill Education |
| record_format | marc |
| spelling | Ünsalan, Cem 1973- Verfasser (DE-588)1253535868 aut Digital system design with FPGA implementation using Verilog and VHDL Cem Ünsalan, Bora Tar New York, NY McGraw-Hill Education [2017] xv, 384 Seiten Illustrationen, Diagramme 25 cm txt rdacontent n rdamedia nc rdacarrier Literaturverzeichnis Seite 369-371 Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s VERILOG (DE-588)4268385-3 s VHDL (DE-588)4254792-1 s DE-604 Tar, Bora ca. 20./21. Jh. Verfasser (DE-588)1260088367 aut V:DE-603;B:DE-17 application/pdf http://scans.hebis.de/HEBCGI/show.pl?41893090_toc.pdf Inhaltsverzeichnis |
| spellingShingle | Ünsalan, Cem 1973- Tar, Bora ca. 20./21. Jh Digital system design with FPGA implementation using Verilog and VHDL Field programmable gate array (DE-588)4347749-5 gnd VHDL (DE-588)4254792-1 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4254792-1 (DE-588)4268385-3 |
| title | Digital system design with FPGA implementation using Verilog and VHDL |
| title_auth | Digital system design with FPGA implementation using Verilog and VHDL |
| title_exact_search | Digital system design with FPGA implementation using Verilog and VHDL |
| title_full | Digital system design with FPGA implementation using Verilog and VHDL Cem Ünsalan, Bora Tar |
| title_fullStr | Digital system design with FPGA implementation using Verilog and VHDL Cem Ünsalan, Bora Tar |
| title_full_unstemmed | Digital system design with FPGA implementation using Verilog and VHDL Cem Ünsalan, Bora Tar |
| title_short | Digital system design with FPGA |
| title_sort | digital system design with fpga implementation using verilog and vhdl |
| title_sub | implementation using Verilog and VHDL |
| topic | Field programmable gate array (DE-588)4347749-5 gnd VHDL (DE-588)4254792-1 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Field programmable gate array VHDL VERILOG |
| url | http://scans.hebis.de/HEBCGI/show.pl?41893090_toc.pdf |
| work_keys_str_mv | AT unsalancem digitalsystemdesignwithfpgaimplementationusingverilogandvhdl AT tarbora digitalsystemdesignwithfpgaimplementationusingverilogandvhdl |