Models for Large Integrated Circuits:
A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of fou...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1990
|
| Schriftenreihe: | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
103 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned |
| Beschreibung: | 1 Online-Ressource (XIV, 220 p) |
| ISBN: | 9781461315551 |
| DOI: | 10.1007/978-1-4613-1555-1 |
Internformat
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| 520 | |a A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned | ||
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Datensatz im Suchindex
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| author | Dewilde, Patrick Ning, Zhen-Qui |
| author_facet | Dewilde, Patrick Ning, Zhen-Qui |
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| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-search | 621.3 |
| dewey-sort | 3621.3 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4613-1555-1 |
| format | Electronic eBook |
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| id | DE-604.BV045187980 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:11:00Z |
| institution | BVB |
| isbn | 9781461315551 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030577157 |
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| series2 | The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Dewilde, Patrick Verfasser aut Models for Large Integrated Circuits by Patrick Dewilde, Zhen-Qui Ning Boston, MA Springer US 1990 1 Online-Ressource (XIV, 220 p) txt rdacontent c rdamedia cr rdacarrier The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 103 A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned Engineering Electrical Engineering Signal, Image and Speech Processing Electrical engineering Mathematisches Modell (DE-588)4114528-8 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Mathematisches Modell (DE-588)4114528-8 s 1\p DE-604 Ning, Zhen-Qui aut Erscheint auch als Druck-Ausgabe 9781461288336 https://doi.org/10.1007/978-1-4613-1555-1 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Dewilde, Patrick Ning, Zhen-Qui Models for Large Integrated Circuits Engineering Electrical Engineering Signal, Image and Speech Processing Electrical engineering Mathematisches Modell (DE-588)4114528-8 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4114528-8 (DE-588)4117388-0 |
| title | Models for Large Integrated Circuits |
| title_auth | Models for Large Integrated Circuits |
| title_exact_search | Models for Large Integrated Circuits |
| title_full | Models for Large Integrated Circuits by Patrick Dewilde, Zhen-Qui Ning |
| title_fullStr | Models for Large Integrated Circuits by Patrick Dewilde, Zhen-Qui Ning |
| title_full_unstemmed | Models for Large Integrated Circuits by Patrick Dewilde, Zhen-Qui Ning |
| title_short | Models for Large Integrated Circuits |
| title_sort | models for large integrated circuits |
| topic | Engineering Electrical Engineering Signal, Image and Speech Processing Electrical engineering Mathematisches Modell (DE-588)4114528-8 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Engineering Electrical Engineering Signal, Image and Speech Processing Electrical engineering Mathematisches Modell VLSI |
| url | https://doi.org/10.1007/978-1-4613-1555-1 |
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