Neural Models and Algorithms for Digital Testing:
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . ....
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1991
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
140 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. 5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . 147 12. 3. 2 Circuit Modeling 148 12 |
| Beschreibung: | 1 Online-Ressource (XIII, 184 p) |
| ISBN: | 9781461539582 |
| DOI: | 10.1007/978-1-4615-3958-2 |
Internformat
MARC
| LEADER | 00000nmm a2200000zcb4500 | ||
|---|---|---|---|
| 001 | BV045187937 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180912s1991 |||| o||u| ||||||eng d | ||
| 020 | |a 9781461539582 |9 978-1-4615-3958-2 | ||
| 024 | 7 | |a 10.1007/978-1-4615-3958-2 |2 doi | |
| 035 | |a (ZDB-2-ENG)978-1-4615-3958-2 | ||
| 035 | |a (OCoLC)1053827578 | ||
| 035 | |a (DE-599)BVBBV045187937 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 | ||
| 082 | 0 | |a 620.00420285 |2 23 | |
| 100 | 1 | |a Chakradhar, Srimat T. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Neural Models and Algorithms for Digital Testing |c by Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushneil |
| 264 | 1 | |a Boston, MA |b Springer US |c 1991 | |
| 300 | |a 1 Online-Ressource (XIII, 184 p) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |v 140 | |
| 520 | |a References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. | ||
| 520 | |a 5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . | ||
| 520 | |a 147 12. 3. 2 Circuit Modeling 148 12 | ||
| 650 | 4 | |a Computer Science | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Electrical Engineering | |
| 650 | 4 | |a Computer science | |
| 650 | 4 | |a Computer-aided engineering | |
| 650 | 4 | |a Electrical engineering | |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Neuronales Netz |0 (DE-588)4226127-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitales Messgerät |0 (DE-588)4123064-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Algorithmus |0 (DE-588)4001183-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Prüftechnik |0 (DE-588)4047610-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitaltechnik |0 (DE-588)4012303-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
| 689 | 0 | 1 | |a Prüftechnik |0 (DE-588)4047610-8 |D s |
| 689 | 0 | 2 | |a Digitales Messgerät |0 (DE-588)4123064-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a Digitaltechnik |0 (DE-588)4012303-0 |D s |
| 689 | 1 | 1 | |a Prüftechnik |0 (DE-588)4047610-8 |D s |
| 689 | 1 | 2 | |a Neuronales Netz |0 (DE-588)4226127-2 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 689 | 2 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 2 | 1 | |a Prüftechnik |0 (DE-588)4047610-8 |D s |
| 689 | 2 | 2 | |a Digitales Messgerät |0 (DE-588)4123064-4 |D s |
| 689 | 2 | |8 3\p |5 DE-604 | |
| 689 | 3 | 0 | |a Neuronales Netz |0 (DE-588)4226127-2 |D s |
| 689 | 3 | 1 | |a Algorithmus |0 (DE-588)4001183-5 |D s |
| 689 | 3 | |8 4\p |5 DE-604 | |
| 700 | 1 | |a Agrawal, Vishwani D. |4 aut | |
| 700 | 1 | |a Bushneil, Michael L. |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9781461367673 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4615-3958-2 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 940 | 1 | |q ZDB-2-ENG_Archiv | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030577114 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 4\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-1-4615-3958-2 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804178880643203072 |
|---|---|
| any_adam_object | |
| author | Chakradhar, Srimat T. Agrawal, Vishwani D. Bushneil, Michael L. |
| author_facet | Chakradhar, Srimat T. Agrawal, Vishwani D. Bushneil, Michael L. |
| author_role | aut aut aut |
| author_sort | Chakradhar, Srimat T. |
| author_variant | s t c st stc v d a vd vda m l b ml mlb |
| building | Verbundindex |
| bvnumber | BV045187937 |
| collection | ZDB-2-ENG |
| ctrlnum | (ZDB-2-ENG)978-1-4615-3958-2 (OCoLC)1053827578 (DE-599)BVBBV045187937 |
| dewey-full | 620.00420285 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 620 - Engineering and allied operations |
| dewey-raw | 620.00420285 |
| dewey-search | 620.00420285 |
| dewey-sort | 3620.00420285 |
| dewey-tens | 620 - Engineering and allied operations |
| doi_str_mv | 10.1007/978-1-4615-3958-2 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>05355nmm a2200805zcb4500</leader><controlfield tag="001">BV045187937</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180912s1991 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781461539582</subfield><subfield code="9">978-1-4615-3958-2</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4615-3958-2</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-1-4615-3958-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1053827578</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045187937</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">620.00420285</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Chakradhar, Srimat T.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Neural Models and Algorithms for Digital Testing</subfield><subfield code="c">by Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushneil</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XIII, 184 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing</subfield><subfield code="v">140</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. </subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . </subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">147 12. 3. 2 Circuit Modeling 148 12</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer Science</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer science</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-aided engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Neuronales Netz</subfield><subfield code="0">(DE-588)4226127-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitales Messgerät</subfield><subfield code="0">(DE-588)4123064-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Algorithmus</subfield><subfield code="0">(DE-588)4001183-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Digitales Messgerät</subfield><subfield code="0">(DE-588)4123064-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="2"><subfield code="a">Neuronales Netz</subfield><subfield code="0">(DE-588)4226127-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Prüftechnik</subfield><subfield code="0">(DE-588)4047610-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="2"><subfield code="a">Digitales Messgerät</subfield><subfield code="0">(DE-588)4123064-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Neuronales Netz</subfield><subfield code="0">(DE-588)4226127-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="1"><subfield code="a">Algorithmus</subfield><subfield code="0">(DE-588)4001183-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="8">4\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Agrawal, Vishwani D.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Bushneil, Michael L.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9781461367673</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4615-3958-2</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_Archiv</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030577114</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">4\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4615-3958-2</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV045187937 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:11:00Z |
| institution | BVB |
| isbn | 9781461539582 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030577114 |
| oclc_num | 1053827578 |
| open_access_boolean | |
| owner | DE-634 |
| owner_facet | DE-634 |
| physical | 1 Online-Ressource (XIII, 184 p) |
| psigel | ZDB-2-ENG ZDB-2-ENG_Archiv ZDB-2-ENG ZDB-2-ENG_Archiv |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| publisher | Springer US |
| record_format | marc |
| series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Chakradhar, Srimat T. Verfasser aut Neural Models and Algorithms for Digital Testing by Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushneil Boston, MA Springer US 1991 1 Online-Ressource (XIII, 184 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 140 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. 5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . 147 12. 3. 2 Circuit Modeling 148 12 Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Neuronales Netz (DE-588)4226127-2 gnd rswk-swf Digitales Messgerät (DE-588)4123064-4 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 s Prüftechnik (DE-588)4047610-8 s Digitales Messgerät (DE-588)4123064-4 s 1\p DE-604 Digitaltechnik (DE-588)4012303-0 s Neuronales Netz (DE-588)4226127-2 s 2\p DE-604 Integrierte Schaltung (DE-588)4027242-4 s 3\p DE-604 Algorithmus (DE-588)4001183-5 s 4\p DE-604 Agrawal, Vishwani D. aut Bushneil, Michael L. aut Erscheint auch als Druck-Ausgabe 9781461367673 https://doi.org/10.1007/978-1-4615-3958-2 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Chakradhar, Srimat T. Agrawal, Vishwani D. Bushneil, Michael L. Neural Models and Algorithms for Digital Testing Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering Integrierte Schaltung (DE-588)4027242-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Neuronales Netz (DE-588)4226127-2 gnd Digitales Messgerät (DE-588)4123064-4 gnd Algorithmus (DE-588)4001183-5 gnd Prüftechnik (DE-588)4047610-8 gnd Digitaltechnik (DE-588)4012303-0 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4131023-8 (DE-588)4226127-2 (DE-588)4123064-4 (DE-588)4001183-5 (DE-588)4047610-8 (DE-588)4012303-0 |
| title | Neural Models and Algorithms for Digital Testing |
| title_auth | Neural Models and Algorithms for Digital Testing |
| title_exact_search | Neural Models and Algorithms for Digital Testing |
| title_full | Neural Models and Algorithms for Digital Testing by Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushneil |
| title_fullStr | Neural Models and Algorithms for Digital Testing by Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushneil |
| title_full_unstemmed | Neural Models and Algorithms for Digital Testing by Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushneil |
| title_short | Neural Models and Algorithms for Digital Testing |
| title_sort | neural models and algorithms for digital testing |
| topic | Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering Integrierte Schaltung (DE-588)4027242-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Neuronales Netz (DE-588)4226127-2 gnd Digitales Messgerät (DE-588)4123064-4 gnd Algorithmus (DE-588)4001183-5 gnd Prüftechnik (DE-588)4047610-8 gnd Digitaltechnik (DE-588)4012303-0 gnd |
| topic_facet | Computer Science Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer science Computer-aided engineering Electrical engineering Integrierte Schaltung Logische Schaltung Neuronales Netz Digitales Messgerät Algorithmus Prüftechnik Digitaltechnik |
| url | https://doi.org/10.1007/978-1-4615-3958-2 |
| work_keys_str_mv | AT chakradharsrimatt neuralmodelsandalgorithmsfordigitaltesting AT agrawalvishwanid neuralmodelsandalgorithmsfordigitaltesting AT bushneilmichaell neuralmodelsandalgorithmsfordigitaltesting |