Sequential Logic Testing and Verification:
In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the in...
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| Main Authors: | , , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA
Springer US
1992
|
| Series: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
163 |
| Subjects: | |
| Online Access: | BTU01 Volltext |
| Summary: | In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance |
| Physical Description: | 1 Online-Ressource (XIX, 214 p) |
| ISBN: | 9781461536468 |
| DOI: | 10.1007/978-1-4615-3646-8 |
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Record in the Search Index
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| author | Ghosh, Abhijit Devadas, Srinivas Newton, A. Richard |
| author_facet | Ghosh, Abhijit Devadas, Srinivas Newton, A. Richard |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:11:00Z |
| institution | BVB |
| isbn | 9781461536468 |
| language | English |
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| series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Ghosh, Abhijit Verfasser aut Sequential Logic Testing and Verification by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton Boston, MA Springer US 1992 1 Online-Ressource (XIX, 214 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 163 In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltwerk (DE-588)4052057-2 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s Test (DE-588)4059549-3 s 1\p DE-604 Schaltwerk (DE-588)4052057-2 s Testen (DE-588)4367264-4 s 2\p DE-604 Logischer Entwurf (DE-588)4168051-0 s 3\p DE-604 Devadas, Srinivas aut Newton, A. Richard aut Erscheint auch als Druck-Ausgabe 9781461366225 https://doi.org/10.1007/978-1-4615-3646-8 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Ghosh, Abhijit Devadas, Srinivas Newton, A. Richard Sequential Logic Testing and Verification Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltwerk (DE-588)4052057-2 gnd Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd Logischer Entwurf (DE-588)4168051-0 gnd Testen (DE-588)4367264-4 gnd Test (DE-588)4059549-3 gnd |
| subject_GND | (DE-588)4052057-2 (DE-588)4131023-8 (DE-588)4121208-3 (DE-588)4168051-0 (DE-588)4367264-4 (DE-588)4059549-3 |
| title | Sequential Logic Testing and Verification |
| title_auth | Sequential Logic Testing and Verification |
| title_exact_search | Sequential Logic Testing and Verification |
| title_full | Sequential Logic Testing and Verification by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| title_fullStr | Sequential Logic Testing and Verification by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| title_full_unstemmed | Sequential Logic Testing and Verification by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| title_short | Sequential Logic Testing and Verification |
| title_sort | sequential logic testing and verification |
| topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltwerk (DE-588)4052057-2 gnd Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd Logischer Entwurf (DE-588)4168051-0 gnd Testen (DE-588)4367264-4 gnd Test (DE-588)4059549-3 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Schaltwerk Logische Schaltung Entwurf Logischer Entwurf Testen Test |
| url | https://doi.org/10.1007/978-1-4615-3646-8 |
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