Modeling of Electrical Overstress in Integrated Circuits:
Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1995
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science
289 |
| Schlagworte: | |
| Online-Zugang: | BTU01 URL des Erstveröffentlichers |
| Zusammenfassung: | Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields |
| Beschreibung: | 1 Online-Ressource (XXV, 148 p) |
| ISBN: | 9781461527886 |
| DOI: | 10.1007/978-1-4615-2788-6 |
Internformat
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| 520 | |a Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields | ||
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| author | Díaz, Carlos H. Kang, Sung-Mo Duvvury, Charvaka |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| isbn | 9781461527886 |
| language | English |
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| spelling | Díaz, Carlos H. Verfasser aut Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury Boston, MA Springer US 1995 1 Online-Ressource (XXV, 148 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science 289 Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Elektrostatische Entladung (DE-588)4401020-5 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s Elektrostatische Entladung (DE-588)4401020-5 s 1\p DE-604 Kang, Sung-Mo aut Duvvury, Charvaka aut Erscheint auch als Druck-Ausgabe 9781461362050 https://doi.org/10.1007/978-1-4615-2788-6 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Díaz, Carlos H. Kang, Sung-Mo Duvvury, Charvaka Modeling of Electrical Overstress in Integrated Circuits Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Integrierte Schaltung (DE-588)4027242-4 gnd Elektrostatische Entladung (DE-588)4401020-5 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4401020-5 |
| title | Modeling of Electrical Overstress in Integrated Circuits |
| title_auth | Modeling of Electrical Overstress in Integrated Circuits |
| title_exact_search | Modeling of Electrical Overstress in Integrated Circuits |
| title_full | Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury |
| title_fullStr | Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury |
| title_full_unstemmed | Modeling of Electrical Overstress in Integrated Circuits by Carlos H. Díaz, Sung-Mo Kang, Charvaka Duvvury |
| title_short | Modeling of Electrical Overstress in Integrated Circuits |
| title_sort | modeling of electrical overstress in integrated circuits |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Integrierte Schaltung (DE-588)4027242-4 gnd Elektrostatische Entladung (DE-588)4401020-5 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Integrierte Schaltung Elektrostatische Entladung |
| url | https://doi.org/10.1007/978-1-4615-2788-6 |
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