Hot-Carrier Reliability of MOS VLSI Circuits:
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis an...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
1993
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing
227 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
| Zusammenfassung: | As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation |
| Beschreibung: | 1 Online-Ressource (XVII, 212 p) |
| ISBN: | 9781461532507 |
| DOI: | 10.1007/978-1-4615-3250-7 |
Internformat
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| 520 | |a As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation | ||
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Datensatz im Suchindex
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| any_adam_object | |
| author | Leblebici, Yusuf Kang, Sung-Mo (Steve) |
| author_facet | Leblebici, Yusuf Kang, Sung-Mo (Steve) |
| author_role | aut aut |
| author_sort | Leblebici, Yusuf |
| author_variant | y l yl s m s k sms smsk |
| building | Verbundindex |
| bvnumber | BV045185037 |
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| ctrlnum | (ZDB-2-ENG)978-1-4615-3250-7 (OCoLC)1053815227 (DE-599)BVBBV045185037 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-3250-7 |
| format | Electronic eBook |
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| id | DE-604.BV045185037 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:54Z |
| institution | BVB |
| isbn | 9781461532507 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030574215 |
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| physical | 1 Online-Ressource (XVII, 212 p) |
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| publishDate | 1993 |
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| series2 | The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing |
| spelling | Leblebici, Yusuf Verfasser aut Hot-Carrier Reliability of MOS VLSI Circuits by Yusuf Leblebici, Sung-Mo (Steve) Kang Boston, MA Springer US 1993 1 Online-Ressource (XVII, 212 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 227 As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits MOS (DE-588)4130209-6 gnd rswk-swf Heißes Elektron (DE-588)4159455-1 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Mathematisches Modell (DE-588)4114528-8 gnd rswk-swf Zuverlässigkeit (DE-588)4059245-5 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Heißes Elektron (DE-588)4159455-1 s MOS (DE-588)4130209-6 s VLSI (DE-588)4117388-0 s 1\p DE-604 Zuverlässigkeit (DE-588)4059245-5 s 2\p DE-604 Mathematisches Modell (DE-588)4114528-8 s 3\p DE-604 Integrierte Schaltung (DE-588)4027242-4 s 4\p DE-604 Kang, Sung-Mo (Steve) aut Erscheint auch als Druck-Ausgabe 9781461364290 https://doi.org/10.1007/978-1-4615-3250-7 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Leblebici, Yusuf Kang, Sung-Mo (Steve) Hot-Carrier Reliability of MOS VLSI Circuits Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits MOS (DE-588)4130209-6 gnd Heißes Elektron (DE-588)4159455-1 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Mathematisches Modell (DE-588)4114528-8 gnd Zuverlässigkeit (DE-588)4059245-5 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4130209-6 (DE-588)4159455-1 (DE-588)4027242-4 (DE-588)4114528-8 (DE-588)4059245-5 (DE-588)4117388-0 |
| title | Hot-Carrier Reliability of MOS VLSI Circuits |
| title_auth | Hot-Carrier Reliability of MOS VLSI Circuits |
| title_exact_search | Hot-Carrier Reliability of MOS VLSI Circuits |
| title_full | Hot-Carrier Reliability of MOS VLSI Circuits by Yusuf Leblebici, Sung-Mo (Steve) Kang |
| title_fullStr | Hot-Carrier Reliability of MOS VLSI Circuits by Yusuf Leblebici, Sung-Mo (Steve) Kang |
| title_full_unstemmed | Hot-Carrier Reliability of MOS VLSI Circuits by Yusuf Leblebici, Sung-Mo (Steve) Kang |
| title_short | Hot-Carrier Reliability of MOS VLSI Circuits |
| title_sort | hot carrier reliability of mos vlsi circuits |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits MOS (DE-588)4130209-6 gnd Heißes Elektron (DE-588)4159455-1 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Mathematisches Modell (DE-588)4114528-8 gnd Zuverlässigkeit (DE-588)4059245-5 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits MOS Heißes Elektron Integrierte Schaltung Mathematisches Modell Zuverlässigkeit VLSI |
| url | https://doi.org/10.1007/978-1-4615-3250-7 |
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