Design of High-Performance CMOS Voltage-Controlled Oscillators:
Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in c...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2003
|
| Schriftenreihe: | The Springer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing
708 |
| Schlagworte: | |
| Online-Zugang: | FHI01 BTU01 URL des Erstveröffentlichers |
| Zusammenfassung: | Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present |
| Beschreibung: | 1 Online-Ressource (XIX, 158 p) |
| ISBN: | 9781461511458 |
| DOI: | 10.1007/978-1-4615-1145-8 |
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| author | Dai, Liang Harjani, Ramesh |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4615-1145-8 |
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| id | DE-604.BV045148895 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:10:02Z |
| institution | BVB |
| isbn | 9781461511458 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030538594 |
| oclc_num | 1050947291 |
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| physical | 1 Online-Ressource (XIX, 158 p) |
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| publisher | Springer US |
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| series2 | The Springer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing |
| spelling | Dai, Liang Verfasser aut Design of High-Performance CMOS Voltage-Controlled Oscillators by Liang Dai, Ramesh Harjani Boston, MA Springer US 2003 1 Online-Ressource (XIX, 158 p) txt rdacontent c rdamedia cr rdacarrier The Springer International Series in Engineering and Computer Science, Analog Circuits and Signal Processing 708 Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits Harjani, Ramesh aut Erscheint auch als Druck-Ausgabe 9781461354147 https://doi.org/10.1007/978-1-4615-1145-8 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Dai, Liang Harjani, Ramesh Design of High-Performance CMOS Voltage-Controlled Oscillators Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
| title | Design of High-Performance CMOS Voltage-Controlled Oscillators |
| title_auth | Design of High-Performance CMOS Voltage-Controlled Oscillators |
| title_exact_search | Design of High-Performance CMOS Voltage-Controlled Oscillators |
| title_full | Design of High-Performance CMOS Voltage-Controlled Oscillators by Liang Dai, Ramesh Harjani |
| title_fullStr | Design of High-Performance CMOS Voltage-Controlled Oscillators by Liang Dai, Ramesh Harjani |
| title_full_unstemmed | Design of High-Performance CMOS Voltage-Controlled Oscillators by Liang Dai, Ramesh Harjani |
| title_short | Design of High-Performance CMOS Voltage-Controlled Oscillators |
| title_sort | design of high performance cmos voltage controlled oscillators |
| topic | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Electrical engineering Electronic circuits |
| url | https://doi.org/10.1007/978-1-4615-1145-8 |
| work_keys_str_mv | AT dailiang designofhighperformancecmosvoltagecontrolledoscillators AT harjaniramesh designofhighperformancecmosvoltagecontrolledoscillators |