Static Crosstalk-Noise Analysis: For Deep Sub-Micron Digital Designs
As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cro...
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| Hauptverfasser: | , , |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2004
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| Schlagworte: | |
| Online-Zugang: | FHI01 BTU01 Volltext |
| Zusammenfassung: | As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis |
| Beschreibung: | 1 Online-Ressource (XVIII, 113 p) |
| ISBN: | 9781402080920 |
| DOI: | 10.1007/b117251 |
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| 520 | |a As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis | ||
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Datensatz im Suchindex
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/b117251 |
| format | Electronic eBook |
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| id | DE-604.BV045148677 |
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| indexdate | 2024-07-10T08:10:01Z |
| institution | BVB |
| isbn | 9781402080920 |
| language | English |
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| physical | 1 Online-Ressource (XVIII, 113 p) |
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| publisher | Springer US |
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| spelling | Chen, Pinhong Verfasser aut Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs by Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer Boston, MA Springer US 2004 1 Online-Ressource (XVIII, 113 p) txt rdacontent c rdamedia cr rdacarrier As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits Kirkpatrick, Desmond A. aut Keutzer, Kurt aut Erscheint auch als Druck-Ausgabe 9781402080913 https://doi.org/10.1007/b117251 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Chen, Pinhong Kirkpatrick, Desmond A. Keutzer, Kurt Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits |
| title | Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs |
| title_auth | Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs |
| title_exact_search | Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs |
| title_full | Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs by Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer |
| title_fullStr | Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs by Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer |
| title_full_unstemmed | Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs by Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer |
| title_short | Static Crosstalk-Noise Analysis |
| title_sort | static crosstalk noise analysis for deep sub micron digital designs |
| title_sub | For Deep Sub-Micron Digital Designs |
| topic | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits |
| topic_facet | Engineering Circuits and Systems Electrical Engineering Computer-Aided Engineering (CAD, CAE) and Design Computer-aided engineering Electrical engineering Electronic circuits |
| url | https://doi.org/10.1007/b117251 |
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