Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog
System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabr...
Gespeichert in:
Hauptverfasser: | , |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
2001
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Ausgabe: | Second Edition |
Schlagworte: | |
Online-Zugang: | FHI01 BTU01 Volltext |
Zusammenfassung: | System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL) |
Beschreibung: | 1 Online-Ressource (XXIV, 282 p) |
ISBN: | 9780306476310 |
DOI: | 10.1007/b116575 |
Internformat
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Datensatz im Suchindex
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author | Bening, Lionel Foster, Harry |
author_facet | Bening, Lionel Foster, Harry |
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dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/b116575 |
edition | Second Edition |
format | Electronic eBook |
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institution | BVB |
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language | English |
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spelling | Bening, Lionel Verfasser aut Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog by Lionel Bening, Harry Foster Second Edition Boston, MA Springer US 2001 1 Online-Ressource (XXIV, 282 p) txt rdacontent c rdamedia cr rdacarrier System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon’s revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL) Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits Register-Transfer-Ebene (DE-588)4215789-4 gnd rswk-swf Register-Transfer-Ebene (DE-588)4215789-4 s 1\p DE-604 Foster, Harry aut Erscheint auch als Druck-Ausgabe 9780792373681 https://doi.org/10.1007/b116575 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Bening, Lionel Foster, Harry Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits Register-Transfer-Ebene (DE-588)4215789-4 gnd |
subject_GND | (DE-588)4215789-4 |
title | Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog |
title_auth | Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog |
title_exact_search | Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog |
title_full | Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog by Lionel Bening, Harry Foster |
title_fullStr | Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog by Lionel Bening, Harry Foster |
title_full_unstemmed | Principles of Verifiable RTL Design A functional coding style supporting verification processes in Verilog by Lionel Bening, Harry Foster |
title_short | Principles of Verifiable RTL Design |
title_sort | principles of verifiable rtl design a functional coding style supporting verification processes in verilog |
title_sub | A functional coding style supporting verification processes in Verilog |
topic | Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits Register-Transfer-Ebene (DE-588)4215789-4 gnd |
topic_facet | Engineering Circuits and Systems Computer Hardware Computer-Aided Engineering (CAD, CAE) and Design Electrical Engineering Computer hardware Computer-aided engineering Electrical engineering Electronic circuits Register-Transfer-Ebene |
url | https://doi.org/10.1007/b116575 |
work_keys_str_mv | AT beninglionel principlesofverifiablertldesignafunctionalcodingstylesupportingverificationprocessesinverilog AT fosterharry principlesofverifiablertldesignafunctionalcodingstylesupportingverificationprocessesinverilog |