Design for embedded image processing on FPGAs:
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Singapore
Wiley
2011
|
| Subjects: | |
| Physical Description: | xvi, 482 p., [6] p. of plates |
| ISBN: | 9780470828519 9780470828526 9781118073315 9780470828496 9780470828502 |
Staff View
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV044845987 | ||
| 003 | DE-604 | ||
| 005 | 20180305 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180305s2011 |||| o||u| ||||||eng d | ||
| 020 | |a 9780470828519 |c Online |9 978-0-470-82851-9 | ||
| 020 | |a 9780470828526 |c ePub |9 978-0-470-82852-6 | ||
| 020 | |a 9781118073315 |c Mobi |9 978-1-118-07331-5 | ||
| 020 | |a 9780470828496 |9 978-0-470-82849-6 | ||
| 020 | |a 9780470828502 |c Online |9 978-0-470-82850-2 | ||
| 035 | |a (ZDB-38-ESG)ebr10483240 | ||
| 035 | |a (OCoLC)747426562 | ||
| 035 | |a (DE-599)BVBBV044845987 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.39/9 |2 22 | |
| 100 | 1 | |a Bailey, Donald G. |d 1962- |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Design for embedded image processing on FPGAs |c Donald G. Bailey |
| 264 | 1 | |a Singapore |b Wiley |c 2011 | |
| 300 | |a xvi, 482 p., [6] p. of plates | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 505 | 8 | |a Includes bibliographical references and index | |
| 505 | 8 | |a "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- | |
| 505 | 8 | |a "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- | |
| 650 | 4 | |a Embedded computer systems | |
| 650 | 4 | |a Field programmable gate arrays | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Eingebettetes System |0 (DE-588)4396978-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 1 | |a Eingebettetes System |0 (DE-588)4396978-1 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 912 | |a ZDB-38-ESG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030240849 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Record in the Search Index
| _version_ | 1804178358075916288 |
|---|---|
| any_adam_object | |
| author | Bailey, Donald G. 1962- |
| author_facet | Bailey, Donald G. 1962- |
| author_role | aut |
| author_sort | Bailey, Donald G. 1962- |
| author_variant | d g b dg dgb |
| building | Verbundindex |
| bvnumber | BV044845987 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references and index "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- |
| ctrlnum | (ZDB-38-ESG)ebr10483240 (OCoLC)747426562 (DE-599)BVBBV044845987 |
| dewey-full | 621.39/9 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/9 |
| dewey-search | 621.39/9 |
| dewey-sort | 3621.39 19 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03234nmm a2200457zc 4500</leader><controlfield tag="001">BV044845987</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20180305 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180305s2011 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470828519</subfield><subfield code="c">Online</subfield><subfield code="9">978-0-470-82851-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470828526</subfield><subfield code="c">ePub</subfield><subfield code="9">978-0-470-82852-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781118073315</subfield><subfield code="c">Mobi</subfield><subfield code="9">978-1-118-07331-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470828496</subfield><subfield code="9">978-0-470-82849-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470828502</subfield><subfield code="c">Online</subfield><subfield code="9">978-0-470-82850-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-38-ESG)ebr10483240</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)747426562</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV044845987</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/9</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bailey, Donald G.</subfield><subfield code="d">1962-</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design for embedded image processing on FPGAs</subfield><subfield code="c">Donald G. Bailey</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Singapore</subfield><subfield code="b">Wiley</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xvi, 482 p., [6] p. of plates</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">"Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"--</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">"The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"--</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Embedded computer systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Field programmable gate arrays</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Eingebettetes System</subfield><subfield code="0">(DE-588)4396978-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Eingebettetes System</subfield><subfield code="0">(DE-588)4396978-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-38-ESG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030240849</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV044845987 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:42Z |
| institution | BVB |
| isbn | 9780470828519 9780470828526 9781118073315 9780470828496 9780470828502 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030240849 |
| oclc_num | 747426562 |
| open_access_boolean | |
| physical | xvi, 482 p., [6] p. of plates |
| psigel | ZDB-38-ESG |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Wiley |
| record_format | marc |
| spelling | Bailey, Donald G. 1962- Verfasser aut Design for embedded image processing on FPGAs Donald G. Bailey Singapore Wiley 2011 xvi, 482 p., [6] p. of plates txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- Embedded computer systems Field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s Eingebettetes System (DE-588)4396978-1 s 1\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Bailey, Donald G. 1962- Design for embedded image processing on FPGAs Includes bibliographical references and index "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- Embedded computer systems Field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4396978-1 |
| title | Design for embedded image processing on FPGAs |
| title_auth | Design for embedded image processing on FPGAs |
| title_exact_search | Design for embedded image processing on FPGAs |
| title_full | Design for embedded image processing on FPGAs Donald G. Bailey |
| title_fullStr | Design for embedded image processing on FPGAs Donald G. Bailey |
| title_full_unstemmed | Design for embedded image processing on FPGAs Donald G. Bailey |
| title_short | Design for embedded image processing on FPGAs |
| title_sort | design for embedded image processing on fpgas |
| topic | Embedded computer systems Field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| topic_facet | Embedded computer systems Field programmable gate arrays Field programmable gate array Eingebettetes System |
| work_keys_str_mv | AT baileydonaldg designforembeddedimageprocessingonfpgas |