Specification and verification of systolic arrays:
Circuits and architectures have become more complex in terms of structure, interconnection topology, and data flow. Design correctness has become increasingly significant, as errors in design may result in strenuous debugging, or even in the repetition of a costly manufacturing process. Although cir...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Singapore
World Scientific Pub. Co.
c1999
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| Schlagworte: | |
| Online-Zugang: | FHN01 URL des Erstveroeffentlichers |
| Zusammenfassung: | Circuits and architectures have become more complex in terms of structure, interconnection topology, and data flow. Design correctness has become increasingly significant, as errors in design may result in strenuous debugging, or even in the repetition of a costly manufacturing process. Although circuit simulation has been used traditionally and widely as the technique for checking hardware and architectural designs, it does not guarantee the conformity of designs to specifications. Formal methods therefore become vital in guaranteeing the correctness of designs and have thus received a significant amount of attention in the CAD industry today.This book presents a formal method for specifying and verifying the correctness of systolic array designs. Such architectures are commonly found in the form of accelerators for digital signal, image, and video processing. These arrays can be quite complicated in topology and data flow. In the book, a formalism called STA is defined for these kinds of dynamic environments, with a survey of related techniques. A framework for specification and verification is established. Formal verification techniques to check the correctness of the systolic networks with respect to the algorithmic level specifications are explained. The book also presents a Prolog-based formal design verifier (named VSTA), developed to automate the verification process, as using a general purpose theorem prover is usually extremely time-consuming. Several application examples are included in the book to illustrate how formal techniques and the verifier can be used to automate proofs |
| Beschreibung: | xiii, 112 p. ill., ports |
| ISBN: | 9789812815279 9812815279 |
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| 245 | 1 | 0 | |a Specification and verification of systolic arrays |c Nam Ling, Magdy A Bayoumi |
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| 520 | |a Circuits and architectures have become more complex in terms of structure, interconnection topology, and data flow. Design correctness has become increasingly significant, as errors in design may result in strenuous debugging, or even in the repetition of a costly manufacturing process. Although circuit simulation has been used traditionally and widely as the technique for checking hardware and architectural designs, it does not guarantee the conformity of designs to specifications. Formal methods therefore become vital in guaranteeing the correctness of designs and have thus received a significant amount of attention in the CAD industry today.This book presents a formal method for specifying and verifying the correctness of systolic array designs. Such architectures are commonly found in the form of accelerators for digital signal, image, and video processing. These arrays can be quite complicated in topology and data flow. In the book, a formalism called STA is defined for these kinds of dynamic environments, with a survey of related techniques. A framework for specification and verification is established. Formal verification techniques to check the correctness of the systolic networks with respect to the algorithmic level specifications are explained. The book also presents a Prolog-based formal design verifier (named VSTA), developed to automate the verification process, as using a general purpose theorem prover is usually extremely time-consuming. Several application examples are included in the book to illustrate how formal techniques and the verifier can be used to automate proofs | ||
| 650 | 4 | |a Computer algorithms | |
| 650 | 4 | |a Systolic array circuits / Design and construction | |
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| id | DE-604.BV044636467 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T07:57:49Z |
| institution | BVB |
| isbn | 9789812815279 9812815279 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030034439 |
| oclc_num | 1012657494 |
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| physical | xiii, 112 p. ill., ports |
| psigel | ZDB-124-WOP ZDB-124-WOP FHN_PDA_WOP |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | World Scientific Pub. Co. |
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| spelling | Ling, Nam 1956- Verfasser aut Specification and verification of systolic arrays Nam Ling, Magdy A Bayoumi Singapore World Scientific Pub. Co. c1999 xiii, 112 p. ill., ports txt rdacontent c rdamedia cr rdacarrier Circuits and architectures have become more complex in terms of structure, interconnection topology, and data flow. Design correctness has become increasingly significant, as errors in design may result in strenuous debugging, or even in the repetition of a costly manufacturing process. Although circuit simulation has been used traditionally and widely as the technique for checking hardware and architectural designs, it does not guarantee the conformity of designs to specifications. Formal methods therefore become vital in guaranteeing the correctness of designs and have thus received a significant amount of attention in the CAD industry today.This book presents a formal method for specifying and verifying the correctness of systolic array designs. Such architectures are commonly found in the form of accelerators for digital signal, image, and video processing. These arrays can be quite complicated in topology and data flow. In the book, a formalism called STA is defined for these kinds of dynamic environments, with a survey of related techniques. A framework for specification and verification is established. Formal verification techniques to check the correctness of the systolic networks with respect to the algorithmic level specifications are explained. The book also presents a Prolog-based formal design verifier (named VSTA), developed to automate the verification process, as using a general purpose theorem prover is usually extremely time-consuming. Several application examples are included in the book to illustrate how formal techniques and the verifier can be used to automate proofs Computer algorithms Systolic array circuits / Design and construction Integrated circuits / Verification Bayoumi, Magdy A. Sonstige oth Erscheint auch als Druck-Ausgabe 9789810238674 Erscheint auch als Druck-Ausgabe 9810238673 http://www.worldscientific.com/worldscibooks/10.1142/4095#t=toc Verlag URL des Erstveroeffentlichers Volltext |
| spellingShingle | Ling, Nam 1956- Specification and verification of systolic arrays Computer algorithms Systolic array circuits / Design and construction Integrated circuits / Verification |
| title | Specification and verification of systolic arrays |
| title_auth | Specification and verification of systolic arrays |
| title_exact_search | Specification and verification of systolic arrays |
| title_full | Specification and verification of systolic arrays Nam Ling, Magdy A Bayoumi |
| title_fullStr | Specification and verification of systolic arrays Nam Ling, Magdy A Bayoumi |
| title_full_unstemmed | Specification and verification of systolic arrays Nam Ling, Magdy A Bayoumi |
| title_short | Specification and verification of systolic arrays |
| title_sort | specification and verification of systolic arrays |
| topic | Computer algorithms Systolic array circuits / Design and construction Integrated circuits / Verification |
| topic_facet | Computer algorithms Systolic array circuits / Design and construction Integrated circuits / Verification |
| url | http://www.worldscientific.com/worldscibooks/10.1142/4095#t=toc |
| work_keys_str_mv | AT lingnam specificationandverificationofsystolicarrays AT bayoumimagdya specificationandverificationofsystolicarrays |