Design recipes for FPGAs: using Verilog and VHDL
This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Writ...
Gespeichert in:
1. Verfasser: | |
---|---|
Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Amsterdam
Newnes is an imprint of Elsevier
2016
|
Ausgabe: | Second edition |
Schlagworte: | |
Online-Zugang: | FAW01 FLA01 Volltext |
Zusammenfassung: | This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create 'real world' designs that fit the device required and which are fast and reliable to implement |
Beschreibung: | Includes bibliographical references and index |
Beschreibung: | 1 online resource illustrations |
ISBN: | 9780080971360 0080971369 9780080971292 0080971296 |
Internformat
MARC
LEADER | 00000nmm a2200000zc 4500 | ||
---|---|---|---|
001 | BV044392094 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 170630s2016 |||| o||u| ||||||eng d | ||
020 | |a 9780080971360 |9 978-0-08-097136-0 | ||
020 | |a 0080971369 |9 0-08-097136-9 | ||
020 | |a 9780080971292 |9 978-0-08-097129-2 | ||
020 | |a 0080971296 |9 0-08-097129-6 | ||
020 | |a 9780080971292 |9 978-0-08-097129-2 | ||
035 | |a (ZDB-33-ESD)ocn922698101 | ||
035 | |a (OCoLC)922698101 | ||
035 | |a (DE-599)BVBBV044392094 | ||
040 | |a DE-604 |b ger |e rda | ||
041 | 0 | |a eng | |
049 | |a DE-1046 | ||
082 | 0 | |a 621.395 |2 23 | |
084 | |a ST 170 |0 (DE-625)143602: |2 rvk | ||
084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
100 | 1 | |a Wilson, Peter R. |d 1939- |e Verfasser |4 aut | |
245 | 1 | 0 | |a Design recipes for FPGAs |b using Verilog and VHDL |c Peter Wilson |
250 | |a Second edition | ||
264 | 1 | |a Amsterdam |b Newnes is an imprint of Elsevier |c 2016 | |
264 | 4 | |c © 2016 | |
300 | |a 1 online resource |b illustrations | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
500 | |a Includes bibliographical references and index | ||
520 | |a This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create 'real world' designs that fit the device required and which are fast and reliable to implement | ||
650 | 7 | |a TECHNOLOGY & ENGINEERING / Mechanical |2 bisacsh | |
650 | 7 | |a Field programmable gate arrays / Design and construction |2 fast | |
650 | 4 | |a Field programmable gate arrays |x Design and construction | |
650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
689 | 0 | 1 | |a VERILOG |0 (DE-588)4268385-3 |D s |
689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |a Wilson, Peter |t Design recipes for FPGAs |b Second edition |d Amsterdam, [Netherlands] : Newnes, c2016 |h xix, 369 pages |z 9780080971292 |
856 | 4 | 0 | |u http://www.sciencedirect.com/science/book/9780080971292 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-33-ESD |a ZDB-33-EBS | ||
999 | |a oai:aleph.bib-bvb.de:BVB01-029794316 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u http://www.sciencedirect.com/science/book/9780080971292 |l FAW01 |p ZDB-33-ESD |q FAW_PDA_ESD |x Verlag |3 Volltext | |
966 | e | |u http://www.sciencedirect.com/science/book/9780080971292 |l FLA01 |p ZDB-33-ESD |q FLA_PDA_ESD |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804177666027290624 |
---|---|
any_adam_object | |
author | Wilson, Peter R. 1939- |
author_facet | Wilson, Peter R. 1939- |
author_role | aut |
author_sort | Wilson, Peter R. 1939- |
author_variant | p r w pr prw |
building | Verbundindex |
bvnumber | BV044392094 |
classification_rvk | ST 170 ST 250 |
collection | ZDB-33-ESD ZDB-33-EBS |
ctrlnum | (ZDB-33-ESD)ocn922698101 (OCoLC)922698101 (DE-599)BVBBV044392094 |
dewey-full | 621.395 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.395 |
dewey-search | 621.395 |
dewey-sort | 3621.395 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
edition | Second edition |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03197nmm a2200589zc 4500</leader><controlfield tag="001">BV044392094</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">170630s2016 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080971360</subfield><subfield code="9">978-0-08-097136-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080971369</subfield><subfield code="9">0-08-097136-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080971292</subfield><subfield code="9">978-0-08-097129-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080971296</subfield><subfield code="9">0-08-097129-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080971292</subfield><subfield code="9">978-0-08-097129-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-33-ESD)ocn922698101</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)922698101</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV044392094</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1046</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.395</subfield><subfield code="2">23</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 170</subfield><subfield code="0">(DE-625)143602:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wilson, Peter R.</subfield><subfield code="d">1939-</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design recipes for FPGAs</subfield><subfield code="b">using Verilog and VHDL</subfield><subfield code="c">Peter Wilson</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Second edition</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam</subfield><subfield code="b">Newnes is an imprint of Elsevier</subfield><subfield code="c">2016</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2016</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource</subfield><subfield code="b">illustrations</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create 'real world' designs that fit the device required and which are fast and reliable to implement</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Mechanical</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Field programmable gate arrays / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Field programmable gate arrays</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="a">Wilson, Peter</subfield><subfield code="t">Design recipes for FPGAs</subfield><subfield code="b">Second edition</subfield><subfield code="d">Amsterdam, [Netherlands] : Newnes, c2016</subfield><subfield code="h">xix, 369 pages</subfield><subfield code="z">9780080971292</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://www.sciencedirect.com/science/book/9780080971292</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-33-ESD</subfield><subfield code="a">ZDB-33-EBS</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-029794316</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://www.sciencedirect.com/science/book/9780080971292</subfield><subfield code="l">FAW01</subfield><subfield code="p">ZDB-33-ESD</subfield><subfield code="q">FAW_PDA_ESD</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://www.sciencedirect.com/science/book/9780080971292</subfield><subfield code="l">FLA01</subfield><subfield code="p">ZDB-33-ESD</subfield><subfield code="q">FLA_PDA_ESD</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV044392094 |
illustrated | Illustrated |
indexdate | 2024-07-10T07:51:42Z |
institution | BVB |
isbn | 9780080971360 0080971369 9780080971292 0080971296 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029794316 |
oclc_num | 922698101 |
open_access_boolean | |
owner | DE-1046 |
owner_facet | DE-1046 |
physical | 1 online resource illustrations |
psigel | ZDB-33-ESD ZDB-33-EBS ZDB-33-ESD FAW_PDA_ESD ZDB-33-ESD FLA_PDA_ESD |
publishDate | 2016 |
publishDateSearch | 2016 |
publishDateSort | 2016 |
publisher | Newnes is an imprint of Elsevier |
record_format | marc |
spelling | Wilson, Peter R. 1939- Verfasser aut Design recipes for FPGAs using Verilog and VHDL Peter Wilson Second edition Amsterdam Newnes is an imprint of Elsevier 2016 © 2016 1 online resource illustrations txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create 'real world' designs that fit the device required and which are fast and reliable to implement TECHNOLOGY & ENGINEERING / Mechanical bisacsh Field programmable gate arrays / Design and construction fast Field programmable gate arrays Design and construction VHDL (DE-588)4254792-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s VERILOG (DE-588)4268385-3 s VHDL (DE-588)4254792-1 s 1\p DE-604 Erscheint auch als Druck-Ausgabe Wilson, Peter Design recipes for FPGAs Second edition Amsterdam, [Netherlands] : Newnes, c2016 xix, 369 pages 9780080971292 http://www.sciencedirect.com/science/book/9780080971292 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Wilson, Peter R. 1939- Design recipes for FPGAs using Verilog and VHDL TECHNOLOGY & ENGINEERING / Mechanical bisacsh Field programmable gate arrays / Design and construction fast Field programmable gate arrays Design and construction VHDL (DE-588)4254792-1 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd |
subject_GND | (DE-588)4254792-1 (DE-588)4347749-5 (DE-588)4268385-3 |
title | Design recipes for FPGAs using Verilog and VHDL |
title_auth | Design recipes for FPGAs using Verilog and VHDL |
title_exact_search | Design recipes for FPGAs using Verilog and VHDL |
title_full | Design recipes for FPGAs using Verilog and VHDL Peter Wilson |
title_fullStr | Design recipes for FPGAs using Verilog and VHDL Peter Wilson |
title_full_unstemmed | Design recipes for FPGAs using Verilog and VHDL Peter Wilson |
title_short | Design recipes for FPGAs |
title_sort | design recipes for fpgas using verilog and vhdl |
title_sub | using Verilog and VHDL |
topic | TECHNOLOGY & ENGINEERING / Mechanical bisacsh Field programmable gate arrays / Design and construction fast Field programmable gate arrays Design and construction VHDL (DE-588)4254792-1 gnd Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd |
topic_facet | TECHNOLOGY & ENGINEERING / Mechanical Field programmable gate arrays / Design and construction Field programmable gate arrays Design and construction VHDL Field programmable gate array VERILOG |
url | http://www.sciencedirect.com/science/book/9780080971292 |
work_keys_str_mv | AT wilsonpeterr designrecipesforfpgasusingverilogandvhdl |