System-on-chip test architectures: nanometer design for testability
Gespeichert in:
| Format: | Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Morgan Kaufmann Publishers
c2008
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | xxxvi, 856 p. |
| ISBN: | 9780123739735 012373973X |
Internformat
MARC
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| 245 | 1 | 0 | |a System-on-chip test architectures |b nanometer design for testability |c edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| 264 | 1 | |a Amsterdam |b Morgan Kaufmann Publishers |c c2008 | |
| 300 | |a xxxvi, 856 p. | ||
| 336 | |b txt |2 rdacontent | ||
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| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Morgan Kaufmann series in systems on silicon | |
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| 650 | 4 | |a Systems on a chip |x Testing | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Testing | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
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| 700 | 1 | |a Touba, Nur A. |e Sonstige |4 oth | |
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Datensatz im Suchindex
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| bvnumber | BV044128389 |
| classification_rvk | ST 150 |
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| ctrlnum | (ZDB-30-PAD)EBC330094 (ZDB-89-EBL)EBL330094 (OCoLC)437198372 (DE-599)BVBBV044128389 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| genre | (DE-588)4173536-5 Patentschrift gnd-content |
| genre_facet | Patentschrift |
| id | DE-604.BV044128389 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:44:32Z |
| institution | BVB |
| isbn | 9780123739735 012373973X |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029535234 |
| oclc_num | 437198372 |
| open_access_boolean | |
| physical | xxxvi, 856 p. |
| psigel | ZDB-30-PAD |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba Amsterdam Morgan Kaufmann Publishers c2008 xxxvi, 856 p. txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes bibliographical references and index Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)4173536-5 Patentschrift gnd-content VLSI (DE-588)4117388-0 s 1\p DE-604 Wang, Laung-Terng Sonstige oth Stroud, Charles E. Sonstige oth Touba, Nur A. Sonstige oth Erscheint auch als Druck-Ausgabe, Hardcover 978-0-12-373973-5 Erscheint auch als Druck-Ausgabe, Hardcover 0-12-373973-X 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | System-on-chip test architectures nanometer design for testability Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4173536-5 |
| title | System-on-chip test architectures nanometer design for testability |
| title_auth | System-on-chip test architectures nanometer design for testability |
| title_exact_search | System-on-chip test architectures nanometer design for testability |
| title_full | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| title_fullStr | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| title_full_unstemmed | System-on-chip test architectures nanometer design for testability edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
| title_short | System-on-chip test architectures |
| title_sort | system on chip test architectures nanometer design for testability |
| title_sub | nanometer design for testability |
| topic | Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd |
| topic_facet | Systems on a chip Testing Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI Patentschrift |
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