Radecka, K. (2003). Verification by error modeling: Using testing techniques in hardware verification. Kluwer Academic Publishers.
Chicago-Zitierstil (17. Ausg.)Radecka, Katarzyna. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Boston: Kluwer Academic Publishers, 2003.
MLA-Zitierstil (9. Ausg.)Radecka, Katarzyna. Verification by Error Modeling: Using Testing Techniques in Hardware Verification. Kluwer Academic Publishers, 2003.
Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.