Low power VLSI design: fundamentals
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| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Berlin
De Gruyter Oldenbourg
[2016]
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Physical Description: | XIV, 310 Seiten Illustrationen |
| ISBN: | 9783110455267 3110455269 |
Staff View
MARC
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| 020 | |a 3110455269 |9 3-11-045526-9 | ||
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| 245 | 1 | 0 | |a Low power VLSI design |b fundamentals |c Angsuman Sarkar [und 3 andere] |
| 264 | 1 | |a Berlin |b De Gruyter Oldenbourg |c [2016] | |
| 300 | |a XIV, 310 Seiten |b Illustrationen | ||
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| 700 | 1 | |a De, Swapnadip |e Sonstige |4 oth | |
| 700 | 1 | |a Chanda, Manash |e Sonstige |4 oth | |
| 700 | 1 | |a Sarkar, Chandan Kumar |e Sonstige |4 oth | |
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Record in the Search Index
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| adam_text | CONTENTS
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2 .11.1
2 .11.2
2.11.3
2
.
11.4
2.11.5
2
.
11.6
2.11.7
INTRODUCTION TO LOW POWER ISSUES IN VLSI
*
1
INTRODUCTION TO VLSI * 1
LOW POWER IC DESIGN BEYOND SUB-20 NM TECHNOLOGY* 2
ISSUES RELATED TO SI* CON MANUFACTURABILITY AND VARIATION *
ISSUES RELATED TO DESIGN PRODUCTIVITY * 4
LIMITATION FACED BY CMOS * 4
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS *
DIFFERENT GROUPS OFMOSFETS* 8*
THREE MOS TYPES* *
LOW LEAKAGE MOSFET* -9
IMPORTANCE OF SUBTHRESHOLD SLOPE* 10
WHY IS SUBTHRESHOLD CURRENT EXPONENTIAL IN NATURE?
* *
SUBTHRESHOLD LEAKAGE AND VOLTAGE LIMITS _ 15
IMPORTANCE OF SUBTHRESHOLD SLOPE IN LOW POWER OPERATION
ULTRALOW VOLTAGE OPERATION _ 1 6
LOW POWER ANALOG CIRCUIT DESIGN * 17
FUNDAMENTAL CONSEQUENCE OF LOWERING SUPPLY VOLTAGE *
ANALOG MOS TRANSISTOR PERFORMANCE PARAMETERS * 19
SUMMARY * 21
REFERENCES * 22
SCALING AND SHORT CHANNEL EFFECTS IN MOSFET * 24
MOSFET SCALING* 24
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS *
GATE OXIDE SCALING* 25
GATE LEAKAGE CURRENT * 25
MOBILITY * 26
H*GH-IC GATE DIEIECTRICS
*
26
KEY GUIDELINES FOR SELECTING AN ALTERNATIVE GATE DIELECTRIC-
MATERIALS * 26
GATE TUNNELING CURRENT * 27
GATE LENGTH SCALING * 27
INTRODUCTION TO SHORT CHANNEL EFFECT IN MOSFET* 27*
REDUCTION OF EFFECTIVE THRESHOLD VOLTAGE* 28*
DRAIN-INDUCED BARRIER LOWERING * 28
MOBILITY DEGRADATION AND SURFACE SCATTE*I N G ~ 3 0
SURFACE SCATTERING* 32
HOT CARRIER EFFECT* 32
PIINRHITHRONGH EFFECT * 32
VELOCITY SATURATION FFFPRT****
5
16 *
*
18
24
26
-
2.11.8 INCREASE IN OFF-STATE LEAKAGE CURRENT * 34
2.12 MOTIVATION FOR PRESENT RESEARCH * 34
2.12.1 LIGHTLY DOPED DRAIN STRUCTURE * 35
2.12.2 CHANNEL ENGINEERING TECHNIQUE * 36
2.12.3 GATE ENGINEERING TECHNIQUE* 3
*
2.12.4 SINGLE HALO DUAL MATERIAL GATE MOSFET* 37*
2.12.5 DOUBLE *** DUAL MATERIAL GATE MOSFET* 38
2.12.6 DOUBLE GATE MOSFET* 38
2.12.7 DUAL MATERIAL DOUBLE GATE MOSFET* 40*
2.12.8 TRIPLE MATERIAL DOUBLE GATE MOSFET* 41
2.12.9 FINFET* 41
2.12.10 TRIPLE GATE MOSFET43* *
2.12.11 GATE-ALL-AROUND MOSFET* 43
2.12.12 SURROUNDING GATE MOSFET* 43*
2.12.13 SILICON NANOWIRES * 44
2.13 FRINGING-INDUCED BARRIER LOWERING** *5
2.14 SILLCON*ON*LNSULATOR MOSFETS ~ 45
2.15 NONCONVENTIONAL DOUBLE GATE MOSFETS * 46
2.16 TUNNE* FIELD-EFFECT TRANSISTOR*
2.17 IMOS DEVICE* -6 5
2.18 SUMMARY * 65
REFERENCES * 66
3 ADVANCED ENERGY-REDUCED CMOS INVERTER DESIGN * 71
3.1 INTRODUCTION * 71
3.1.1 TRANSFER CHARACTERISTICS OF INVERTER* 71
3.1.2 STATIC CMOS INVERTER IN SUPER-THRESHOLD REGIME * 73
3.1.3 INTRODUCTION TO SUBTHRESHOLD LOGIC * 94
3.1.4 SUMMARY * 107
REFERENCES * *
4 ADVANCED COMBINATIONAL CIRCUIT DESIGN * 112
INTRODUCTION* 112
4.1 STATIC CMOS LOGIC GATE DESIGN * 112
4.2 COMPLEMENTARY PROPERTIES OF CMOS LOGIC* 112
4.2.1 CMOS NAND GATE * 113
4.2.2 CMOS NOR GATE * 113
4.2.3 SOME MORE EXAMPLES OF CMOS LOGIC * 115
4.2.4 XOR OR NONEQUIVALENCE GATE USING CMOS LOGIC * 116
4.2.5 X0R-XN0R OR EQUIVALENCE GATE USING CMOS LOGIC * 116
4.2.6 AND*OR*LNVERT AND OR*AND*LNVERT G ATES* 117
4.2.7 FU* ADDER CIRCUITS USING CMOS LOGIC * 118
4.3 PSEUDO-NMOS G ATES* 120*
4.3.1 WHY THE NAME IS PSEUDO.NMOS?* 123*
4.3.2 RATLOED LOGIC* .123
4.3.3 OPERATION OFPSEUDO-NMOS INVERTER* 12*
4.4 PASS-TRANSISTOR LOGIC* 125
4.5 COMPLEMENTARY PASS TRANSISTOR LOGIC127 ***
4.6 SIGNAL RESTORING PASS TRANSISTOR LOGIC DESIGN * 128
4.7 SIZING OF TRANSISTOR IN CMOS DESIGN STYLE** 129
4.8 INTRODUCTION TO LOGICAL EFFORT * 132
4.8.1 DEFINITIONS OF LOGICAL EFFORT* .132
4.9 DELAY ESTIMATION BY LOGICAL EFFORT* 135
*1* INTRODUCTION TO TRANSMISSION GATE * 136
4.10.1 USE OF CMOS *6 AS SWITCH * 138
4.10.2 2:1 MULTIPLEXER USING TG * 141
4.10.3 XORGATE USING TG * 141
4.10.4 XNORGATE USING TG * 143
*1
*
* TRANSMISSION GATE ADDERS * 144
4.10.6 MORE EXAMPLES OF TG LOGIC * 144
4.11 TRISTATE BUFFER * 145
*-19 TRANSMISSION GATES AND TRISTATES* 146
4.13 IMPLEMENTATION OF COMBINATIONAL CIRCUIT USING DTMOS LOGIC FOR
ULTRALOW POWER APPLICATION * 149
4.14 ECLR STRUCTURE * 154
4.14.1 POWER CONSUMPTION * 175
4.14.2 PROPAGATION DELAY * 175
REFERENCES * 175
5 ADVANCED ENERGY-REDUCED SEQUENTIAL CIRCUIT
DESIGN* 177
5.1 INTRODUCTION TO SEQUENTIAL CIRCUIT* 177*
5.2 BASICS OF REGENERATIVE SIRRNITQ**177
5.3 BASIC SR F* P-FLOP/**ATCH * 181
5.3.1 NAND GATE-BASED NEGATIVE LOGIC
SR
LATCH * 183
5.3.2 CLOCKED
SR
LATCH * 183
5.4 A
*
CKED/K
*
LATCH* 185*
5.4.1 TOGGLE SWITCH* 186*
5.5 M ASTER-SLAVE FLIP-FLOP * 186
5.6 D LATCH* 187*
5.6.1 POSITIVE AND NEGATIVE LATCH188* *
5.6.2 MULTIPLEXER-BASED LATCH * 188
5.7 M ASTER-SLAVE EDGE-TRIGGERED FLIP-FLOPS * 190
5.8 TIMING PARAMETERS FOR SEQUENTIAL CIRCUITS * 192
5.8.1 TIMING OF MULTIPLEXER-BASED MASTER-SLAVE FLIP
*** * 194
** * COTENTS
5.8.2 THE SIZING REQUIREMENTS FOR THE TRANSMISSION
GATES * 195
5.9 CLOCK SKEWS DUE TO NONIDEAL **** SIGNAL * 196
5.10 DESIGN AND ANALYSIS OF THE F* P-FL
0
PS USING DTMOS STYLE * 197
5.10.1 5/? LATCH AND FLIP-FLOP * 197
5.10.2
JK
LATCH AND
JK
FLIP-FLOP * 201
5.10.3 * FLIP-FLOP * 202
5.11 ADIABATIC FLIP-FLOP * 205
REFERENCES * 207
6 INTRODUCTION TO MEMORY DESIGN * 208
INTRODUCTION208* *
6.1 TYPES OF SEMICONDUCTOR MEMORY * 208
6.2 MEMOY ORGANIZATION * 210
6.3 INTRODUCTION TO DRAM * 212 *
6.4 ONE*TRANSISTOR **** SPLI
* *
213
6.4.1 WRITE * 214
6.4.2 HOLD
* *
2W
6.4.3 READ * 215
6.5 CAPACITOR IN D L * 217
6.6 REFRESH OPERATION OF DRAM * 219
6.7 DRAM TYPES * 220
6.7.1 FPM DRAMS * 220
6.7.2 EXTENDED DATA OUT DRAMS * 221
6.7.3 BURST EDO DRAMS221* *
6.7.4 ARAM * 221
6.7.5 CACHE DRAM * 221
6.7.6 FNHANRPH **** (FNPAM)*- 1 * *
6.7.7 SYNCHRONOUS DRAM * 222
6.7.8 D U B LE DATA READ NPAMC* - * * *
6.7.9 SYNCHRONOUS GRAPHIC RAM * 222
6.7.10 ENHANCED SYNCHRONOUS DRAMS * 222
^711 VIDEODRAMS * 223
6.7.12 WINDOW D I S * 223
6.7.13 PSEUDO-STATIC RAMS * 223
6.7.14 RAMBUS DRAMS * 223
6.7.15 MULTIBANK D L * 224
6.7.16 FERROELECTRIC D * 224
6.8 SOI D I * 225
6.8.1 OPERATING PRINCIPLE * 225
6.8.2 DESIGN CONSIDERATIONS OF SOI DRAM* 226
6.9 INTRODUCTION TO SRAM * 226
6.10
6.11
6.12
6
.
12.1
6
.
12.2
6.13
6.14
6.15
6.16
6.17
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.35
7.3.6
7.3.7
7.38
7.3.9
7.3.10
7.3.11
7.3.12
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.5.1
7.6
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.7
SRAM CELL AND ITS OPERATION
*
227
S I CE* FAILURES * 228
PERFORMANCE METRICS OF SRAM * 228
STATIC NOISE MARGIN
*
228
RELIABILITY ISSUES OF 6-* SRAM * 229
READ-ONLY MEMORY* 230
EPROM * 3*
ELECTRICALLY ERASABLE PROGRAMMABLE READONLY MEMORY (E2PR0M)
*
2 4 *
HASH MEMORY * 236
SUMMARY * 238
REFERENCES * 239
ANALOG LOW POWER VLSI CIRCUIT DESIGN - 242
ANALOG LOW POWER DESIGN: PROBLEMS WITH TRANSISTOR MISMATCH * 242
MIXED-SIGNAL DESIGN WITH SUB-100 NM TECHNOLOGY* * *
CHALLENGES IN MS DESIGN IN SUB.100 NM SPACE * 244
LACK OF CONVERGENCE OFTECHNOLOGY * 244
DIGITAL SCALING* 245
MEMORY SCALING* * 6
ANALOG SCALING* * 7
DEGRADED SNR * 247
DEGRADATION IN INTRINSIC GAIN
*
248
DEVICE LEAKAGE * * 8
MISMATCH DUE TO REDUCED MATCHING* .2 4 8
AVAILAHLILTY OF MODELS * 248
PASSIVES * M E
RF SCALING * * 9
ISSUES RELATED
WITH
POWER DEVICES * 250
BASICS OF SWITCHED-CAPACITOR CIRCUITS * 250
RESISTOR EMULATION USING S C NETWORK * 251
INTEGRATOR USING S C CIRCUITS * 252
SC INTEGRATOR SENSITIVE TO PA*AS** C _ 2 5 5
LOW POWER SWITCHED.CAPACITOR CIRCUIT
_
256
CURRENT SOURCE/SINK * 258
TECHNIQUE TO INCREASE OUTPUT RESISTANCE * 261
LOW POWER CURRENT MIRROR
*
263
USE OF CURRENT MIRRORS IN
* *
263
SIMPLE CURRENT MIRROR * 265
WILSON CURRENT MIRROR* 267
CASCODE CURRENT MIRROR * 268
LOW VOLTAGE CURRENT MIRROR* 270*
FUNDAMENTALS OF CURRENT/VOLTAGE REFERENCE * 273
7.7.1
7.8
7.8.1
7.8.2
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.10
7.11
INDEX
ANOTHER WAY TO OBTAIN SIMPLE BOOTSTRAP VOLTAGE REFERENCE
CIRCUIT
WITH
S TARTUP CIRCUIT*
279*
BANDGAP VOLTAGE REFERENCE * 282
POSITIVE TC VOLTAGE * 282
NEGATIVE TC VOLTAGE * 283
AN INTRODUCTION TO ANALOG DESIGN AUTOMATION * 284
SURVEY OF PREVIOUS ANALOG DESIGN FLOW
*
285
ANALOG AND MIXED-SIGNAL DESIGN PROCESS * 288
HIERARCHICAL ANALOG DESIGN METHODOLOGY * 290
CURRENT STATUS FOR THE MAIN TASKS IN ANALOG DESIGN
AUTOMATION * 292
FIELD-PROGRAMMABLE ANALOG ARRAYS * 299
SUMMARY * 301
REFERENCES* 301*
305
|
| any_adam_object | 1 |
| author | Sarkar, Angsuman |
| author_facet | Sarkar, Angsuman |
| author_role | aut |
| author_sort | Sarkar, Angsuman |
| author_variant | a s as |
| building | Verbundindex |
| bvnumber | BV044039874 |
| classification_rvk | ZN 4950 |
| ctrlnum | (OCoLC)932645293 (DE-599)DNB1079802770 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV044039874 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T07:41:54Z |
| institution | BVB |
| institution_GND | (DE-588)1065492103 |
| isbn | 9783110455267 3110455269 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029446945 |
| oclc_num | 932645293 |
| open_access_boolean | |
| owner | DE-703 |
| owner_facet | DE-703 |
| physical | XIV, 310 Seiten Illustrationen |
| publishDate | 2016 |
| publishDateSearch | 2016 |
| publishDateSort | 2016 |
| publisher | De Gruyter Oldenbourg |
| record_format | marc |
| spelling | Low power VLSI design fundamentals Angsuman Sarkar [und 3 andere] Berlin De Gruyter Oldenbourg [2016] XIV, 310 Seiten Illustrationen txt rdacontent n rdamedia nc rdacarrier Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Schaltwerk (DE-588)4052057-2 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Schaltnetz (DE-588)4052053-5 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Halbleiterspeicher (DE-588)4120419-0 gnd rswk-swf Kurzkanal-FET (DE-588)4207298-0 gnd rswk-swf Power-Management (DE-588)7738882-3 gnd rswk-swf VLSI (DE-588)4117388-0 s CMOS (DE-588)4010319-5 s Digitale integrierte Schaltung (DE-588)4113313-4 s Analoge integrierte Schaltung (DE-588)4112519-8 s Entwurfsautomation (DE-588)4312536-0 s Power-Management (DE-588)7738882-3 s Kurzkanal-FET (DE-588)4207298-0 s Schaltnetz (DE-588)4052053-5 s Schaltwerk (DE-588)4052057-2 s Halbleiterspeicher (DE-588)4120419-0 s DE-604 Sarkar, Angsuman aut De, Swapnadip Sonstige oth Chanda, Manash Sonstige oth Sarkar, Chandan Kumar Sonstige oth De Gruyter Oldenbourg (DE-588)1065492103 pbl Erscheint auch als Online-Ausgabe, PDF 978-3-11-045529-8 Erscheint auch als Online-Ausgabe, EPUB 978-3-11-045555-7 Erscheint auch als Online-Ausgabe Sarkar Low Power VLSI Design B:DE-101 application/pdf http://d-nb.info/1079802770/04 Inhaltsverzeichnis DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029446945&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Sarkar, Angsuman Low power VLSI design fundamentals Digitale integrierte Schaltung (DE-588)4113313-4 gnd Schaltwerk (DE-588)4052057-2 gnd Entwurfsautomation (DE-588)4312536-0 gnd Schaltnetz (DE-588)4052053-5 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd CMOS (DE-588)4010319-5 gnd VLSI (DE-588)4117388-0 gnd Halbleiterspeicher (DE-588)4120419-0 gnd Kurzkanal-FET (DE-588)4207298-0 gnd Power-Management (DE-588)7738882-3 gnd |
| subject_GND | (DE-588)4113313-4 (DE-588)4052057-2 (DE-588)4312536-0 (DE-588)4052053-5 (DE-588)4112519-8 (DE-588)4010319-5 (DE-588)4117388-0 (DE-588)4120419-0 (DE-588)4207298-0 (DE-588)7738882-3 |
| title | Low power VLSI design fundamentals |
| title_auth | Low power VLSI design fundamentals |
| title_exact_search | Low power VLSI design fundamentals |
| title_full | Low power VLSI design fundamentals Angsuman Sarkar [und 3 andere] |
| title_fullStr | Low power VLSI design fundamentals Angsuman Sarkar [und 3 andere] |
| title_full_unstemmed | Low power VLSI design fundamentals Angsuman Sarkar [und 3 andere] |
| title_short | Low power VLSI design |
| title_sort | low power vlsi design fundamentals |
| title_sub | fundamentals |
| topic | Digitale integrierte Schaltung (DE-588)4113313-4 gnd Schaltwerk (DE-588)4052057-2 gnd Entwurfsautomation (DE-588)4312536-0 gnd Schaltnetz (DE-588)4052053-5 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd CMOS (DE-588)4010319-5 gnd VLSI (DE-588)4117388-0 gnd Halbleiterspeicher (DE-588)4120419-0 gnd Kurzkanal-FET (DE-588)4207298-0 gnd Power-Management (DE-588)7738882-3 gnd |
| topic_facet | Digitale integrierte Schaltung Schaltwerk Entwurfsautomation Schaltnetz Analoge integrierte Schaltung CMOS VLSI Halbleiterspeicher Kurzkanal-FET Power-Management |
| url | http://d-nb.info/1079802770/04 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029446945&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT sarkarangsuman lowpowervlsidesignfundamentals AT deswapnadip lowpowervlsidesignfundamentals AT chandamanash lowpowervlsidesignfundamentals AT sarkarchandankumar lowpowervlsidesignfundamentals AT degruyteroldenbourg lowpowervlsidesignfundamentals |
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