Advanced model order reduction techniques in VLSI design:
Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world example...
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| Main Author: | |
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| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cambridge
Cambridge University Press
2007
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| Subjects: | |
| Online Access: | BSB01 FHN01 Volltext |
| Summary: | Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry |
| Item Description: | Title from publisher's bibliographic system (viewed on 05 Oct 2015) |
| Physical Description: | 1 online resource (xviii, 240 pages) |
| ISBN: | 9780511541117 |
| DOI: | 10.1017/CBO9780511541117 |
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| 505 | 8 | |a List of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index | |
| 520 | |a Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry | ||
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| author_facet | Tan, Sheldon X. D. |
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| contents | List of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index |
| ctrlnum | (ZDB-20-CBO)CR9780511541117 (OCoLC)850190931 (DE-599)BVBBV043945732 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1017/CBO9780511541117 |
| format | Electronic eBook |
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| id | DE-604.BV043945732 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:39:24Z |
| institution | BVB |
| isbn | 9780511541117 |
| language | English |
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| physical | 1 online resource (xviii, 240 pages) |
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| publishDate | 2007 |
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| publisher | Cambridge University Press |
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| spelling | Tan, Sheldon X. D. Verfasser aut Advanced model order reduction techniques in VLSI design Sheldon X.-D. Tan, Lei He Cambridge Cambridge University Press 2007 1 online resource (xviii, 240 pages) txt rdacontent c rdamedia cr rdacarrier Title from publisher's bibliographic system (viewed on 05 Oct 2015) List of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This 2007 book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry Integrated circuits / Very large scale integration / Design He, Lei Sonstige oth Erscheint auch als Druckausgabe 978-0-521-86581-4 Erscheint auch als Druckausgabe 978-1-107-41154-8 https://doi.org/10.1017/CBO9780511541117 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Tan, Sheldon X. D. Advanced model order reduction techniques in VLSI design List of figures; List of tables; Preface; 1. Introduction; 2. Projection-based model order reduction algorithms; 3. Truncated balanced realization methods for model order reduction; 4. Passive balanced truncation of linear systems in descriptor form; 5. Passive hierarchical model order reduction; 6. Terminal reduction of linear dynamic circuits; 7. Vector potential equivalent circuit for inductance modeling; 8. Structure-preserving model order reduction; 9. Block structure-preserving reduction for RLCK circuits; 10. Model optimization and passivity enforcement; 11. General multi-port circuit realization; 12. Model order reduction for multi-terminal linear dynamic circuits; 13. Passive modeling by signal waveform shaping; References; Index Integrated circuits / Very large scale integration / Design |
| title | Advanced model order reduction techniques in VLSI design |
| title_auth | Advanced model order reduction techniques in VLSI design |
| title_exact_search | Advanced model order reduction techniques in VLSI design |
| title_full | Advanced model order reduction techniques in VLSI design Sheldon X.-D. Tan, Lei He |
| title_fullStr | Advanced model order reduction techniques in VLSI design Sheldon X.-D. Tan, Lei He |
| title_full_unstemmed | Advanced model order reduction techniques in VLSI design Sheldon X.-D. Tan, Lei He |
| title_short | Advanced model order reduction techniques in VLSI design |
| title_sort | advanced model order reduction techniques in vlsi design |
| topic | Integrated circuits / Very large scale integration / Design |
| topic_facet | Integrated circuits / Very large scale integration / Design |
| url | https://doi.org/10.1017/CBO9780511541117 |
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