ESD design and synthesis - Voldman, Steven H. (Wiley, 2011)
Includes bibliographical references and index
"The book focuses on both fundamentals of ESD design to construct and integrate a semiconductor chip. It enables ESD engineers to build better products by exploring six key areas- 1) ESD design synthesis 2) I/O design and integration 3) semiconductor chip architecture 4) floor planning 5) power bus design and 6) ESD power clamps. The book is well organised and uses a top down approach, starting by looking at the basics. It takes a look at design synthesis, floor planning and ESD design issues. The book analyses the synthesis of device elements, also the synthesis of ESD circuits and functional circuits. In Chapter 5, the synthesis of ESD power clamps is described, followed by coverage on synthesis of power rails with I/O, ESD and pads in Chapter 6. The integration of special function circuits and special issues is helpfully included in the book before more broad ESD design methodioligies are outlined. The important areas of design rule checking, along with design verification methods, are looked at towards the end of the book, and the last chapter provides the reader with knowledge about useful design tools. In many ways this text is unique. There is currently no other book on the market that addresses ESD design synthesis and its relationaship to the characterisation of test structures and technologies. Focuses on practical design techniques, providing good design practices and rules contains essential information on chip floor-planning and architecture that has not been published in a single book before covers up-to-date technology benchmarking and characterisation uses state-of-the-art examples with detailed discussion includes end-of-chapter design and integration problems"--
Machine generated contents note - 1 - ESD Design Synthesis -- - 1.1 - ESD Design Synthesis and Architecture Flow -- - 1.1.1 - Top-Down ESD Design -- - 1.1.2 - Bottom-Up ESD Design -- - 1.1.3 - Top-Down ESD Design -- Memory Semiconductor Chips -- - 1.1.4 - Top-Down ESD Design -- ASIC Design System -- - 1.2 - ESD Design -- The Signal Path and the Alternate Current Path -- - 1.3 - ESD Electrical Circuit and Schematic Architecture Concepts -- - 1.3.1 - The Ideal ESD Network and the Current -- Voltage DC Design Window -- - 1.3.2 - The ESD Design Window -- - 1.3.3 - The Ideal ESD Networks in the Frequency Domain Design Window -- - 1.4 - Mapping Semiconductor Chips and ESD Designs -- - 1.4.1 - Mapping Across Semiconductor Fabricators -- - 1.4.2 - ESD Design Mapping Across Technology Generations -- - 1.4.3 - Mapping from Bipolar Technology to CMOS Technology -- - 1.4.4 - Mapping from Digital CMOS Technology to Mixed Signal Analog -- Digital CMOS Technology -- - 1.4.5 - Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI) -- - 1.4.6 - ESD Design -- Mapping CMOS to RF CMOS Technology
1.5 - ESD Chip Architecture and ESD Test Standards -- - 1.5.1 - ESD Chip Architecture and ESD Testing -- - 1.6 - ESD Testing -- - 1.6.1 - ESD Qualification Testing -- - 1.6.2 - ESD Test Models -- - 1.6.3 - ESD Characterization Testing -- - 1.6.4 - TLP Testing -- - 1.7 - ESD Chip Architecture and ESD Alternative Current Paths -- - 1.7.1 - ESD Circuits, I/O, and Cores -- - 1.7.2 - ESD Signal Pin Circuits -- - 1.7.3 - ESD Power Clamp Networks -- - 1.7.4 - ESD Rail-to-Rail Circuits -- - 1.7.5 - ESD Design and Noise -- - 1.7.6 - Internal Signal Path ESD Networks -- - 1.7.7 - Cross-Domain ESD Networks -- - 1.8 - ESD Networks, Sequencing, and Chip Architecture -- - 1.9 - ESD Design Synthesis -- Latchup-Free ESD Networks -- - 1.10 - ESD Design Concepts -- Buffering -- Inter-Device -- - 1.11 - ESD Design Concepts -- Ballasting -- Inter-Device -- - 1.12 - ESD Design Concepts -- Ballasting -- Intra-Device -- - 1.13 - ESD Design Concepts -- Distributed Load Techniques -- - 1.14 - ESD Design Concepts -- Dummy Circuits -- - 1.15 - ESD Design Concepts -- Power Supply De-Coupling -- - 1.16 - ESD Design Concepts -- Feedback Loop De-Coupling -- - 1.17 - ESD Layout and Floorplan-Related Concepts
1.17.1 - Design Symmetry -- - 1.17.2 - Design Segmentation -- - 1.17.3 - ESD Design Concepts -- Utilization of Empty Space -- - 1.17.4 - ESD Design Synthesis -- Across Chip Line Width Variation (ACLV) -- - 1.17.5 - ESD Design Concepts -- Dummy Shapes -- - 1.17.6 - ESD Design Concepts -- Dummy Masks -- - 1.17.7 - ESD Design Concepts -- Adjacency -- - 1.18 - ESD Design Concepts -- Analog Circuit Techniques -- - 1.19 - ESD Design Concepts -- Wire Bonds -- - 1.20 - Design Rules -- - 1.20.1 - ESD Design Rule Checking (DRC) -- - 1.20.2 - ESD Layout vs. Schematic (LVS) -- - 1.20.3 - Electrical Resistance Checking (ERC) -- - 1.21 - Summary and Closing Comments -- - Problems -- - References -- - 2 - ESD Architecture and Floorplanning -- - 2.1 - ESD Design Floorplan -- - 2.2 - Peripheral I/O Design -- - 2.2.1 - Pad-Limited Peripheral I/O Design Architecture -- - 2.2.2 - Pad-Limited Peripheral I/O Design Architecture -- Staggered I/O -- - 2.2.3 - Core-Limited Peripheral I/O Design Architecture -- - 2.3 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture -- - 2.3.1 - Lumped ESD Power Clamp in Peripheral I/O Design Architecture in the Semiconductor Chip Corners