Verification techniques for system-level design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Morgan Kaufmann Publishers
c2008
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Beschreibung: | Includes bibliographical references and index This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Printbegrænsninger: Der kan printes kapitelvis 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion |
| Beschreibung: | 1 Online-Ressource (viii, 240 p.) |
| ISBN: | 0080553133 9780080553139 |
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| 500 | |a Includes bibliographical references and index | ||
| 500 | |a This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology | ||
| 500 | |a Printbegrænsninger: Der kan printes kapitelvis | ||
| 500 | |a 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion | ||
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Datensatz im Suchindex
| _version_ | 1804175493485821952 |
|---|---|
| any_adam_object | |
| author | Fujita, Masahiro |
| author_facet | Fujita, Masahiro |
| author_role | aut |
| author_sort | Fujita, Masahiro |
| author_variant | m f mf |
| building | Verbundindex |
| bvnumber | BV043091834 |
| classification_rvk | ZN 4904 |
| collection | ZDB-4-EBA |
| ctrlnum | (OCoLC)182548558 (DE-599)BVBBV043091834 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV043091834 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:17:10Z |
| institution | BVB |
| isbn | 0080553133 9780080553139 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028516026 |
| oclc_num | 182548558 |
| open_access_boolean | |
| owner | DE-1046 DE-1047 |
| owner_facet | DE-1046 DE-1047 |
| physical | 1 Online-Ressource (viii, 240 p.) |
| psigel | ZDB-4-EBA ZDB-4-EBA FAW_PDA_EBA |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | Fujita, Masahiro Verfasser aut Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad Amsterdam Morgan Kaufmann Publishers c2008 1 Online-Ressource (viii, 240 p.) txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes bibliographical references and index This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Printbegrænsninger: Der kan printes kapitelvis 1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Verification blmlsh Formal methods (Computer science) blmlsh Systems on a chip / Testing local Integrated circuits / Verification local Formal methods (Computer science) local Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip (DE-588)4740357-3 gnd rswk-swf LSI (DE-588)4168200-2 gnd rswk-swf Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf System-on-Chip (DE-588)4740357-3 s LSI (DE-588)4168200-2 s Hardwareverifikation (DE-588)4214982-4 s 1\p DE-604 Ghosh, Indradeep Sonstige oth Prasad, Mukul Sonstige oth Erscheint auch als Druck-Ausgabe, Paperback 0-12-370616-5 Erscheint auch als Druck-Ausgabe, Paperback 978-0-12-370616-4 http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=210385 Aggregator Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Fujita, Masahiro Verification techniques for system-level design TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Verification blmlsh Formal methods (Computer science) blmlsh Systems on a chip / Testing local Integrated circuits / Verification local Formal methods (Computer science) local Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip (DE-588)4740357-3 gnd LSI (DE-588)4168200-2 gnd Hardwareverifikation (DE-588)4214982-4 gnd |
| subject_GND | (DE-588)4740357-3 (DE-588)4168200-2 (DE-588)4214982-4 |
| title | Verification techniques for system-level design |
| title_auth | Verification techniques for system-level design |
| title_exact_search | Verification techniques for system-level design |
| title_full | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_fullStr | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_full_unstemmed | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_short | Verification techniques for system-level design |
| title_sort | verification techniques for system level design |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Systems on a chip / Testing blmlsh Integrated circuits / Verification blmlsh Formal methods (Computer science) blmlsh Systems on a chip / Testing local Integrated circuits / Verification local Formal methods (Computer science) local Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) System-on-Chip (DE-588)4740357-3 gnd LSI (DE-588)4168200-2 gnd Hardwareverifikation (DE-588)4214982-4 gnd |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated TECHNOLOGY & ENGINEERING / Electronics / Circuits / General Systems on a chip / Testing Integrated circuits / Verification Formal methods (Computer science) Systems on a chip Testing Integrated circuits Verification System-on-Chip LSI Hardwareverifikation |
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