Skew-tolerant circuit design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
San Francisco
Morgan Kaufmann Publishers
c2001
|
| Schlagworte: | |
| Online-Zugang: | FAW01 Volltext |
| Beschreibung: | Includes bibliographical references and index As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises |
| Beschreibung: | 1 Online-Ressource (xiv, 223 p.) |
| ISBN: | 0080541267 155860636X 9780080541266 9781558606364 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV042307764 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 150129s2001 |||| o||u| ||||||eng d | ||
| 020 | |a 0080541267 |c electronic bk. |9 0-08-054126-7 | ||
| 020 | |a 155860636X |9 1-55860-636-X | ||
| 020 | |a 155860636X |9 1-55860-636-X | ||
| 020 | |a 9780080541266 |c electronic bk. |9 978-0-08-054126-6 | ||
| 020 | |a 9781558606364 |9 978-1-55860-636-4 | ||
| 035 | |a (OCoLC)647697026 | ||
| 035 | |a (DE-599)BVBBV042307764 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-1046 | ||
| 082 | 0 | |a 621.3815 |2 21 | |
| 100 | 1 | |a Harris, David, (David Lewis) |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Skew-tolerant circuit design |c David Harris |
| 264 | 1 | |a San Francisco |b Morgan Kaufmann Publishers |c c2001 | |
| 300 | |a 1 Online-Ressource (xiv, 223 p.) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 500 | |a As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises | ||
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / General |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Design and construction |2 fast | |
| 650 | 7 | |a Synchronization |2 fast | |
| 650 | 7 | |a Timing circuits / Design and construction |2 fast | |
| 650 | 7 | |a Timing circuits / Design and construction |2 local | |
| 650 | 7 | |a Integrated circuits / Very large scale integration / Design and construction |2 local | |
| 650 | 7 | |a Synchronization |2 local | |
| 650 | 4 | |a Timing circuits |x Design and construction | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 4 | |a Synchronization | |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 653 | |a Electronic books | ||
| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 856 | 4 | 0 | |u http://www.sciencedirect.com/science/book/9781558606364 |x Verlag |3 Volltext |
| 912 | |a ZDB-33-ESD | ||
| 940 | 1 | |q FLA_PDA_ESD | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027744756 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u http://www.sciencedirect.com/science/book/9781558606364 |l FAW01 |p ZDB-33-ESD |q FAW_PDA_ESD |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804152893462282240 |
|---|---|
| any_adam_object | |
| author | Harris, David, (David Lewis) |
| author_facet | Harris, David, (David Lewis) |
| author_role | aut |
| author_sort | Harris, David, (David Lewis) |
| author_variant | d d l h ddl ddlh |
| building | Verbundindex |
| bvnumber | BV042307764 |
| collection | ZDB-33-ESD |
| ctrlnum | (OCoLC)647697026 (DE-599)BVBBV042307764 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03743nmm a2200577zc 4500</leader><controlfield tag="001">BV042307764</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">150129s2001 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0080541267</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">0-08-054126-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">155860636X</subfield><subfield code="9">1-55860-636-X</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">155860636X</subfield><subfield code="9">1-55860-636-X</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080541266</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-0-08-054126-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781558606364</subfield><subfield code="9">978-1-55860-636-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)647697026</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV042307764</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1046</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">21</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Harris, David, (David Lewis)</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Skew-tolerant circuit design</subfield><subfield code="c">David Harris</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">San Francisco</subfield><subfield code="b">Morgan Kaufmann Publishers</subfield><subfield code="c">c2001</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xiv, 223 p.)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / General</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Synchronization</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Timing circuits / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Timing circuits / Design and construction</subfield><subfield code="2">local</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Very large scale integration / Design and construction</subfield><subfield code="2">local</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Synchronization</subfield><subfield code="2">local</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Timing circuits</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronization</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="653" ind1=" " ind2=" "><subfield code="a">Electronic books</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://www.sciencedirect.com/science/book/9781558606364</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-33-ESD</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">FLA_PDA_ESD</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027744756</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://www.sciencedirect.com/science/book/9781558606364</subfield><subfield code="l">FAW01</subfield><subfield code="p">ZDB-33-ESD</subfield><subfield code="q">FAW_PDA_ESD</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV042307764 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:17:57Z |
| institution | BVB |
| isbn | 0080541267 155860636X 9780080541266 9781558606364 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027744756 |
| oclc_num | 647697026 |
| open_access_boolean | |
| owner | DE-1046 |
| owner_facet | DE-1046 |
| physical | 1 Online-Ressource (xiv, 223 p.) |
| psigel | ZDB-33-ESD FLA_PDA_ESD ZDB-33-ESD FAW_PDA_ESD |
| publishDate | 2001 |
| publishDateSearch | 2001 |
| publishDateSort | 2001 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| spelling | Harris, David, (David Lewis) Verfasser aut Skew-tolerant circuit design David Harris San Francisco Morgan Kaufmann Publishers c2001 1 Online-Ressource (xiv, 223 p.) txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. * Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial * Provides incisive instruction and advice punctuated by humorous illustrations * Includes exercises to test understanding of key concepts and solutions to selected exercises TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Integrated circuits / Very large scale integration / Design and construction fast Synchronization fast Timing circuits / Design and construction fast Timing circuits / Design and construction local Integrated circuits / Very large scale integration / Design and construction local Synchronization local Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Electronic books Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 http://www.sciencedirect.com/science/book/9781558606364 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Harris, David, (David Lewis) Skew-tolerant circuit design TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Integrated circuits / Very large scale integration / Design and construction fast Synchronization fast Timing circuits / Design and construction fast Timing circuits / Design and construction local Integrated circuits / Very large scale integration / Design and construction local Synchronization local Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4027242-4 |
| title | Skew-tolerant circuit design |
| title_auth | Skew-tolerant circuit design |
| title_exact_search | Skew-tolerant circuit design |
| title_full | Skew-tolerant circuit design David Harris |
| title_fullStr | Skew-tolerant circuit design David Harris |
| title_full_unstemmed | Skew-tolerant circuit design David Harris |
| title_short | Skew-tolerant circuit design |
| title_sort | skew tolerant circuit design |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / General bisacsh Integrated circuits / Very large scale integration / Design and construction fast Synchronization fast Timing circuits / Design and construction fast Timing circuits / Design and construction local Integrated circuits / Very large scale integration / Design and construction local Synchronization local Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Synchronization Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / Integrated TECHNOLOGY & ENGINEERING / Electronics / Circuits / General Integrated circuits / Very large scale integration / Design and construction Synchronization Timing circuits / Design and construction Timing circuits Design and construction Integrated circuits Very large scale integration Design and construction Integrierte Schaltung |
| url | http://www.sciencedirect.com/science/book/9781558606364 |
| work_keys_str_mv | AT harrisdaviddavidlewis skewtolerantcircuitdesign |