Interconnection networks: an engineering approach
Gespeichert in:
1. Verfasser: | |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
San Francisco, CA
Morgan Kaufmann
c2003
|
Ausgabe: | Rev. print |
Schlagworte: | |
Online-Zugang: | FAW01 Volltext |
Beschreibung: | The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. * Gives a coherent, comprehensive treatment of the entire field * Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs * Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks * Focuses on issues critical to designers Includes bibliographical references (p. 569-592) and index |
Beschreibung: | 1 Online-Ressource (xxiii, 600 p.) |
ISBN: | 1558608524 9781558608528 |
Internformat
MARC
LEADER | 00000nmm a2200000zc 4500 | ||
---|---|---|---|
001 | BV042307438 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 150129s2003 |||| o||u| ||||||eng d | ||
020 | |a 1558608524 |9 1-55860-852-4 | ||
020 | |a 9781558608528 |9 978-1-55860-852-8 | ||
035 | |a (OCoLC)52616057 | ||
035 | |a (DE-599)BVBBV042307438 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-1046 | ||
082 | 0 | |a 004.6 |2 22 | |
100 | 1 | |a Duato, José |e Verfasser |4 aut | |
245 | 1 | 0 | |a Interconnection networks |b an engineering approach |c José Duato, Sudhakar Yalamanchili, Lionel Ni |
250 | |a Rev. print | ||
264 | 1 | |a San Francisco, CA |b Morgan Kaufmann |c c2003 | |
300 | |a 1 Online-Ressource (xxiii, 600 p.) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
500 | |a The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. * Gives a coherent, comprehensive treatment of the entire field * Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs * Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks * Focuses on issues critical to designers | ||
500 | |a Includes bibliographical references (p. 569-592) and index | ||
650 | 7 | |a Redes de computadores |2 larpcal | |
650 | 7 | |a Arquitetura e organização de computadores |2 larpcal | |
650 | 7 | |a Computer networks |2 fast | |
650 | 7 | |a Multiprocessors |2 fast | |
650 | 4 | |a Computer networks | |
650 | 4 | |a Multiprocessors | |
650 | 0 | 7 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Verbindungsstruktur |0 (DE-588)4316956-9 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Rechnernetz |0 (DE-588)4070085-9 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Netzadresse |0 (DE-588)4323072-6 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a Netzadresse |0 (DE-588)4323072-6 |D s |
689 | 0 | 1 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
689 | 1 | 0 | |a Rechnernetz |0 (DE-588)4070085-9 |D s |
689 | 1 | 1 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
689 | 1 | |8 2\p |5 DE-604 | |
689 | 2 | 0 | |a Rechnernetz |0 (DE-588)4070085-9 |D s |
689 | 2 | 1 | |a Verbindungsstruktur |0 (DE-588)4316956-9 |D s |
689 | 2 | |8 3\p |5 DE-604 | |
700 | 1 | |a Yalamanchili, Sudhakar |e Sonstige |4 oth | |
700 | 1 | |a Ni, Lionel M. |e Sonstige |4 oth | |
856 | 4 | 0 | |u http://www.sciencedirect.com/science/book/9781558608528 |x Verlag |3 Volltext |
912 | |a ZDB-33-ESD | ||
940 | 1 | |q FLA_PDA_ESD | |
999 | |a oai:aleph.bib-bvb.de:BVB01-027744430 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u http://www.sciencedirect.com/science/book/9781558608528 |l FAW01 |p ZDB-33-ESD |q FAW_PDA_ESD |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804152892751347712 |
---|---|
any_adam_object | |
author | Duato, José |
author_facet | Duato, José |
author_role | aut |
author_sort | Duato, José |
author_variant | j d jd |
building | Verbundindex |
bvnumber | BV042307438 |
collection | ZDB-33-ESD |
ctrlnum | (OCoLC)52616057 (DE-599)BVBBV042307438 |
dewey-full | 004.6 |
dewey-hundreds | 000 - Computer science, information, general works |
dewey-ones | 004 - Computer science |
dewey-raw | 004.6 |
dewey-search | 004.6 |
dewey-sort | 14.6 |
dewey-tens | 000 - Computer science, information, general works |
discipline | Informatik |
edition | Rev. print |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03795nmm a2200649zc 4500</leader><controlfield tag="001">BV042307438</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">150129s2003 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1558608524</subfield><subfield code="9">1-55860-852-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781558608528</subfield><subfield code="9">978-1-55860-852-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)52616057</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV042307438</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1046</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">004.6</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Duato, José</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Interconnection networks</subfield><subfield code="b">an engineering approach</subfield><subfield code="c">José Duato, Sudhakar Yalamanchili, Lionel Ni</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">Rev. print</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">San Francisco, CA</subfield><subfield code="b">Morgan Kaufmann</subfield><subfield code="c">c2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xxiii, 600 p.)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. * Gives a coherent, comprehensive treatment of the entire field * Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs * Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks * Focuses on issues critical to designers</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references (p. 569-592) and index</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Redes de computadores</subfield><subfield code="2">larpcal</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Arquitetura e organização de computadores</subfield><subfield code="2">larpcal</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Computer networks</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Multiprocessors</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer networks</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Multiprocessors</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Verbindungsstruktur</subfield><subfield code="0">(DE-588)4316956-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Rechnernetz</subfield><subfield code="0">(DE-588)4070085-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Netzadresse</subfield><subfield code="0">(DE-588)4323072-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Netzadresse</subfield><subfield code="0">(DE-588)4323072-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Rechnernetz</subfield><subfield code="0">(DE-588)4070085-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Rechnernetz</subfield><subfield code="0">(DE-588)4070085-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Verbindungsstruktur</subfield><subfield code="0">(DE-588)4316956-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Yalamanchili, Sudhakar</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ni, Lionel M.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://www.sciencedirect.com/science/book/9781558608528</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-33-ESD</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">FLA_PDA_ESD</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027744430</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://www.sciencedirect.com/science/book/9781558608528</subfield><subfield code="l">FAW01</subfield><subfield code="p">ZDB-33-ESD</subfield><subfield code="q">FAW_PDA_ESD</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV042307438 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T01:17:56Z |
institution | BVB |
isbn | 1558608524 9781558608528 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027744430 |
oclc_num | 52616057 |
open_access_boolean | |
owner | DE-1046 |
owner_facet | DE-1046 |
physical | 1 Online-Ressource (xxiii, 600 p.) |
psigel | ZDB-33-ESD FLA_PDA_ESD ZDB-33-ESD FAW_PDA_ESD |
publishDate | 2003 |
publishDateSearch | 2003 |
publishDateSort | 2003 |
publisher | Morgan Kaufmann |
record_format | marc |
spelling | Duato, José Verfasser aut Interconnection networks an engineering approach José Duato, Sudhakar Yalamanchili, Lionel Ni Rev. print San Francisco, CA Morgan Kaufmann c2003 1 Online-Ressource (xxiii, 600 p.) txt rdacontent c rdamedia cr rdacarrier The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. * Gives a coherent, comprehensive treatment of the entire field * Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs * Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks * Focuses on issues critical to designers Includes bibliographical references (p. 569-592) and index Redes de computadores larpcal Arquitetura e organização de computadores larpcal Computer networks fast Multiprocessors fast Computer networks Multiprocessors Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf Verbindungsstruktur (DE-588)4316956-9 gnd rswk-swf Rechnernetz (DE-588)4070085-9 gnd rswk-swf Netzadresse (DE-588)4323072-6 gnd rswk-swf Netzadresse (DE-588)4323072-6 s Mehrprozessorsystem (DE-588)4038397-0 s 1\p DE-604 Rechnernetz (DE-588)4070085-9 s 2\p DE-604 Verbindungsstruktur (DE-588)4316956-9 s 3\p DE-604 Yalamanchili, Sudhakar Sonstige oth Ni, Lionel M. Sonstige oth http://www.sciencedirect.com/science/book/9781558608528 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Duato, José Interconnection networks an engineering approach Redes de computadores larpcal Arquitetura e organização de computadores larpcal Computer networks fast Multiprocessors fast Computer networks Multiprocessors Mehrprozessorsystem (DE-588)4038397-0 gnd Verbindungsstruktur (DE-588)4316956-9 gnd Rechnernetz (DE-588)4070085-9 gnd Netzadresse (DE-588)4323072-6 gnd |
subject_GND | (DE-588)4038397-0 (DE-588)4316956-9 (DE-588)4070085-9 (DE-588)4323072-6 |
title | Interconnection networks an engineering approach |
title_auth | Interconnection networks an engineering approach |
title_exact_search | Interconnection networks an engineering approach |
title_full | Interconnection networks an engineering approach José Duato, Sudhakar Yalamanchili, Lionel Ni |
title_fullStr | Interconnection networks an engineering approach José Duato, Sudhakar Yalamanchili, Lionel Ni |
title_full_unstemmed | Interconnection networks an engineering approach José Duato, Sudhakar Yalamanchili, Lionel Ni |
title_short | Interconnection networks |
title_sort | interconnection networks an engineering approach |
title_sub | an engineering approach |
topic | Redes de computadores larpcal Arquitetura e organização de computadores larpcal Computer networks fast Multiprocessors fast Computer networks Multiprocessors Mehrprozessorsystem (DE-588)4038397-0 gnd Verbindungsstruktur (DE-588)4316956-9 gnd Rechnernetz (DE-588)4070085-9 gnd Netzadresse (DE-588)4323072-6 gnd |
topic_facet | Redes de computadores Arquitetura e organização de computadores Computer networks Multiprocessors Mehrprozessorsystem Verbindungsstruktur Rechnernetz Netzadresse |
url | http://www.sciencedirect.com/science/book/9781558608528 |
work_keys_str_mv | AT duatojose interconnectionnetworksanengineeringapproach AT yalamanchilisudhakar interconnectionnetworksanengineeringapproach AT nilionelm interconnectionnetworksanengineeringapproach |