Digital signal processing with field programmable gate arrays:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Berlin [u.a.]
Springer
2014
|
| Edition: | 4th ed. |
| Series: | Signals and communication technology
|
| Subjects: | |
| Online Access: | Inhaltstext Inhaltsverzeichnis |
| Physical Description: | XXIII, 930 S. Ill., graph. Darst. 1 CD-ROM |
| ISBN: | 9783642453083 9783642453090 3642453082 |
Staff View
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| 245 | 1 | 0 | |a Digital signal processing with field programmable gate arrays |c Uwe Meyer-Baese |
| 250 | |a 4th ed. | ||
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2014 | |
| 300 | |a XXIII, 930 S. |b Ill., graph. Darst. |e 1 CD-ROM | ||
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Record in the Search Index
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| adam_text |
CONTENTS
PREFACE TO FIRST EDITION VII
PREFACE TO SECOND EDITION XI
PREFACE TO THIRD EDITION XIII
PREFACE TO FOURTH EDITION XV
1. INTRODUCTION I
1.1 OVERVIEW OF DIGITAL SIGNAL PROCESSING (DSP) 1
1.2 FPGA TECHNOLOGY 3
1.2.1 CLASSIFICATION BY GRANULARITY 3
1.2.2 CLASSIFICATION BY TECHNOLOGY 6
1.2.3 BENCHMARK FOR FPLS 7
1.3 DSP TECHNOLOGY REQUIREMENTS 12
1.3.1 FPGA AND PROGRAMMABLE SIGNAL PROCESSORS 14
1.4 DESIGN IMPLEMENTATION 15
1.4.1 FPGA STRUCTURE 20
1.4.2 THE ALTERA EP4CE115F29C7 23
1.4.3 CASE STUDY: FREQUENCY SYNTHESIZER 32
1.4.4 DESIGN WITH INTELLECTUAL PROPERTY CORES 40
EXERCISES 47
2. COMPUTER ARITHMETIC 57
2.1 INTRODUCTION 57
2.2 NUMBER REPRESENTATION 58
2.2.1 FIXED-POINT NUMBERS 58
2.2.2 UNCONVENTIONAL FIXED-POINT NUMBERS 61
2.2.3 FLOATING-POINT NUMBERS 75
2.3 BINARY ADDERS 79
2.3.1 PIPELINED ADDERS 81
2.3.2 MODULO ADDERS 85
2.4 BINARY MULTIPLIERS 86
2.4.1 MULTIPLIER BLOCKS 89
HTTP://D-NB.INFO/1044794844
XVIII CONTENTS
2.5 BINARY DIVIDERS 93
2.5.1 LINEAR CONVERGENCE DIVISION ALGORITHMS 95
2.5.2 FAST DIVIDER DESIGN 100
2.5.3 ARRAY DIVIDER 105
2.6 FIXED-POINT ARITHMETIC IMPLEMENTATION 106
2.7 FLOATING-POINT ARITHMETIC IMPLEMENTATION 109
2.7.1 FIXED-POINT TO FLOATING-POINT FORMAT CONVERSION 110
2.7.2 FLOATING-POINT TO FIXED-POINT FORMAT CONVERSION ILL
2.7.3 FLOATING-POINT MULTIPLICATION 112
2.7.4 FLOATING-POINT ADDITION 113
2.7.5 FLOATING-POINT DIVISION 115
2.7.6 FLOATING-POINT RECIPROCAL 116
2.7.7 FLOATING-POINT OPERATION SYNTHESIS 118
2.7.8 FLOATING-POINT SYNTHESIS RESULTS 122
2.8 MULTIPLY-ACCUMULATOR (MAC) AND SUM OF PRODUCT (SOP) . . 124
2.8.1 DISTRIBUTED ARITHMETIC FUNDAMENTALS 125
2.8.2 SIGNED DA SYSTEMS 129
2.8.3 MODIFIED DA SOLUTIONS 130
2.9 COMPUTATION OF SPECIAL FUNCTIONS USING CORDIC 131
2.9.1 CORDIC ARCHITECTURES 135
2.10 COMPUTATION OF SPECIAL FUNCTIONS USING MAC CALLS 141
2.10.1 CHEBYSHEV APPROXIMATIONS 142
2.10.2 TRIGONOMETRIC FUNCTION APPROXIMATION 143
2.10.3 EXPONENTIAL AND LOGARITHMIC FUNCTION APPROXIMATION 152
2.10.4 SQUARE ROOT FUNCTION APPROXIMATION 159
2.10 FAST MAGNITUDE APPROXIMATION 165
EXERCISES 168
3. FINITE IMPULSE RESPONSE (FIR) DIGITAL FILTERS 179
3.1 DIGITAL FILTERS 179
3.2 FIR THEORY 180
3.2.1 FIR FILTER WITH TRANSPOSED STRUCTURE 181
3.2.2 SYMMETRY IN FIR FILTERS 184
3.2.3 LINEAR-PHASE FIR FILTERS 185
3.3 DESIGNING FIR FILTERS 187
3.3.1 DIRECT WINDOW DESIGN METHOD 187
3.3.2 EQUIRIPPLE DESIGN METHOD 190
3.4 CONSTANT COEFFICIENT FIR DESIGN 192
3.4.1 DIRECT FIR DESIGN 192
3.4.2 FIR FILTER WITH TRANSPOSED STRUCTURE 196
3.4.3 FIR FILTERS USING DISTRIBUTED ARITHMETIC 204
3.4.4 IP CORE FIR FILTER DESIGN 215
3.4.5 COMPARISON OF DA- AND RAG-BASED FIR FILTERS 217
EXERCISES 219
CONTENTS XIX
4. INFINITE IMPULSE RESPONSE (HR) DIGITAL FILTERS 225
4.1 IIR THEORY 228
4.2 IIR COEFFICIENT COMPUTATION 231
4.2.1 SUMMARY OF IMPORTANT IIR DESIGN ATTRIBUTES 233
4.3 IIR FILTER IMPLEMENTATION 234
4.3.1 FINITE WORDLENGTH EFFECTS 238
4.3.2 OPTIMIZATION OF THE FILTER GAIN FACTOR 239
4.4 FAST IIR FILTER 240
4.4.1 TIME-DOMAIN INTERLEAVING 241
4.4.2 CLUSTERED AND SCATTERED LOOK-AHEAD PIPELINING 243
4.4.3 IIR DECIMATOR DESIGN 246
4.4.4 PARALLEL PROCESSING 246
4.4.5 IIR DESIGN USING RNS 250
4.5 NARROW BAND IIR FILTER 250
4.5.1 NARROW BAND DESIGN EXAMPLE 251
4.5.2 CASCADE SECOND ORDER SYSTEMS NARROW BAND FILTER
DESIGN 259
4.5.3 PARALLEL SECOND ORDER SYSTEMS NARROW BAND FILTER
DESIGN 263
4.5.4 LATTICE DESIGN OF NARROW BAND IIR FILTER 271
4.5.5 WAVE DIGITAL FILTER DESIGN OF NARROW BAND IIR FILTER. 280
4.6 ALL-PASS FILTER DESIGN OF NARROW BAND IIR FILTER 287
4.6.1 ALL-PASS WAVE DIGITAL FILTER DESIGN OF NARROW BAND
IIR FILTER 289
4.6.2 ALL-PASS LATTICE DESIGN OF NARROW BAND IIR FILTER. . . . 293
4.6.3 ALL-PASS DIRECT FORM DESIGN OF NARROW BAND FILTER. . . 294
4.6.4 ALL-PASS CASCADE BIQUAD OF NARROW BAND FILTER 295
4.6.5 ALL-PASS PARALLEL BIQUAD OF NARROW BAND FILTER 295
EXERCISES 299
5. MULTIRATE SIGNAL PROCESSING 305
5.1 DECIMATION AND INTERPOLATION 305
5.1.1 NOBLE IDENTITIES 306
5.1.2 SAMPLING RATE CONVERSION BY RATIONAL FACTOR 308
5.2 POLYPHASE DECOMPOSITION 309
5.2.1 RECURSIVE IIR DECIMATOR 314
5.2.2 FAST-RUNNING FIR FILTER 315
5.3 HOGENAUER CIC FILTERS 317
5.3.1 SINGLE-STAGE CIC CASE STUDY 317
5.3.2 MULTISTAGE CIC FILTER THEORY 320
5.3.3 AMPLITUDE AND ALIASING DISTORTION 325
5.3.4 HOGENAUER PRUNING THEORY 328
5.3.5 CIC RNS DESIGN 333
5.3.6 CIC COMPENSATION FILTER DESIGN 334
5.4 MULTISTAGE DECIMATOR 337
XX CONTENTS
5.4.1 MULTISTAGE DECIMATOR DESIGN USING GOODMAN-CAREY
HALF-BAND FILTERS 338
5.5 FREQUENCY-SAMPLING FILTERS AS BANDPASS DECIMATORS 341
5.6 DESIGN OF ARBITRARY SAMPLING RATE CONVERTERS 345
5.6.1 FRACTIONAL DELAY RATE CHANGE 349
5.6.2 POLYNOMIAL FRACTIONAL DELAY DESIGN 356
5.6.3 B-SPLINE-BASED FRACTIONAL RATE CHANGER 362
5.6.4 MOMS FRACTIONAL RATE CHANGER 366
5.7 FILTER BANKS 374
5.7.1 UNIFORM DFT FILTER BANK 375
5.7.2 TWO-CHANNEL FILTER BANKS 379
5.8 WAVELETS 395
5.8.1 THE DISCRETE WAVELET TRANSFORMATION 398
5.8.2 DISCRETE WAVELET TRANSFORMATION APPLICATIONS 402
EXERCISES 411
6. FOURIER TRANSFORMS 417
6.1 THE DISCRETE FOURIER TRANSFORM ALGORITHMS 418
6.1.1 FOURIER TRANSFORM APPROXIMATIONS USING THE DFT . . . 418
6.1.2 PROPERTIES OF THE DFT 420
6.1.3 THE GOERTZEL ALGORITHM 423
6.1.4 THE BLUESTEIN CHIRP-Z TRANSFORM 424
6.1.5 THE RADER ALGORITHM 427
6.1.6 THE WINOGRAD DFT ALGORITHM 434
6.2 THE FAST FOURIER TRANSFORM (FFT) ALGORITHMS 436
6.2.1 THE COOLEY-TUKEY FFT ALGORITHM 437
6.2.2 THE GOOD-THOMAS FFT ALGORITHM 449
6.2.3 THE WINOGRAD FFT ALGORITHM 451
6.2.4 COMPARISON OF DFT AND FFT ALGORITHMS 455
6.2.5 IP CORE FFT DESIGN 456
6.3 FOURIER-RELATED TRANSFORMS 461
6.3.1 COMPUTING THE DCT USING THE DFT 462
6.3.2 FAST DIRECT DCT IMPLEMENTATION 463
EXERCISES 465
7. COMMUNICATION SYSTEMS 475
7.1 ERROR CONTROL AND CRYPTOGRAPHY 475
7.1.1 BASIC CONCEPTS FROM CODING THEORY 476
7.1.2 BLOCK CODES 482
7.1.3 CONVOLUTIONAL CODES 485
7.1.4 CRYPTOGRAPHY ALGORITHMS FOR FPGAS 494
7.2 MODULATION AND DEMODULATION 509
7.2.1 BASIC MODULATION CONCEPTS 510
7.2.2 INCOHERENT DEMODULATION 515
7.2.3 COHERENT DEMODULATION 521
CONTENTS XXI
EXERCISES 529
8. ADAPTIVE SYSTEMS 533
8.1 APPLICATION OF ADAPTIVE SYSTEMS 534
8.1.1 INTERFERENCE CANCELLATION 534
8.1.2 PREDICTION 535
8.1.3 INVERSE MODELING 535
8.1.4 SYSTEM IDENTIFICATION 536
8.2 OPTIMUM ESTIMATION TECHNIQUES 537
8.2.1 THE OPTIMUM WIENER ESTIMATION 540
8.3 THE WIDROW-HOFF LEAST MEAN SQUARE ALGORITHM 544
8.3.1 LEARNING CURVES 551
8.3.2 NORMALIZED LMS (NLMS) 554
8.4 TRANSFORM DOMAIN LMS ALGORITHMS 555
8.4.1 FAST-CONVOLUTION TECHNIQUES 556
8.4.2 USING ORTHOGONAL TRANSFORMS 557
8.5 IMPLEMENTATION OF THE LMS ALGORITHM 561
8.5.1 QUANTIZATION EFFECTS 561
8.5.2 FPGA DESIGN OF THE LMS ALGORITHM 561
8.5.3 PIPELINED LMS FILTERS 565
8.5.4 TRANSPOSED FORM LMS FILTER 567
8.5.5 DESIGN OF DLMS ALGORITHMS 568
8.5.6 LMS DESIGNS USING SIGNUM FUNCTION 572
8.6 RECURSIVE LEAST SQUARE ALGORITHMS 575
8.6.1 RLS WITH FINITE MEMORY 578
8.6.2 FAST RLS KALMAN IMPLEMENTATION 581
8.6.3 THE FAST A POSTERIORI KALMAN RLS ALGORITHM 586
8.7 COMPARISON OF LMS AND RLS PARAMETERS 587
8.8 PRINCIPLE COMPONENT ANALYSIS (PCA) 589
8.8.1 PRINCIPLE COMPONENT ANALYSIS COMPUTATION 591
8.8.2 IMPLEMENTATION OF SANGER'S GHA PCA 595
8.9 INDEPENDENT COMPONENT ANALYSIS (ICA) 601
8.9.1 WHITENING AND ORTHOGONALIZATION 603
8.9.2 INDEPENDENT COMPONENT ANALYSIS ALGORITHM 604
8.9.3 IMPLEMENTATION OF THE EASI ICA ALGORITHM 605
8.9.4 ALTERNATIVE BSS ALGORITHMS 610
8.10 CODING OF SPEECH AND AUDIO SIGNALS 612
8.10.1 A- AND ^IT-LAW
CODING 612
8.10.2 LINEAR AND ADAPTIVE PCM CODING 617
8.10.3 CODING BY MODELING: THE LPC-LOE METHOD 623
8.10.4 MPEG AUDIO CODING METHODS 624
EXERCISES 626
XXII CONTENTS
9. MICROPROCESSOR DESIGN 631
9.1 HISTORY OF MICROPROCESSORS 631
9.1.1 BRIEF HISTORY OF GENERAL-PURPOSE MICROPROCESSORS . 632
9.1.2 BRIEF HISTORY OF RISC MICROPROCESSORS 634
9.1.3 BRIEF HISTORY OF PDSPS 635
9.2 INSTRUCTION SET DESIGN 638
9.2.1 ADDRESSING MODES 638
9.2.2 DATA FLOW: ZERO-, ONE-, TWO- OR THREE-ADDRESS DESIGN 646
9.2.3 REGISTER FILE AND MEMORY ARCHITECTURE 652
9.2.4 OPERATION SUPPORT 656
9.2.5 NEXT OPERATION LOCATION 659
9.3 SOFTWARE TOOLS 660
9.3.1 LEXICAL ANALYSIS 661
9.3.2 PARSER DEVELOPMENT 672
9.4 FPGA MICROPROCESSOR CORES 682
9.4.1 HARDCORE MICROPROCESSORS 683
9.4.2 SOFTCORE MICROPROCESSORS 689
9.5 CASE STUDIES 700
9.5.1 T-RISC STACK MICROPROCESSORS 700
9.5.2 LISA WAVELET PROCESSOR DESIGN 706
9.5.3 NIOS CUSTOM INSTRUCTION DESIGN 721
EXERCISES 728
10. IMAGE AND VIDEO PROCESSING 739
10.1 OVERVIEW ON IMAGE AND VIDEO PROCESSING 740
10.1.1 IMAGE FORMAT 741
10.1.2 BASIC IMAGE PROCESSING OPERATION 746
10.2 CASE STUDY 1: EDGE DETECTION IN HDL 748
10.2.1 2D HDL FILTER DESIGN 751
10.2.2 IMAGING SYSTEM DESIGN 753
10.2.3 PUTTING THE VGA EDGE DETECTION SYSTEM TOGETHER . . . 757
10.3 CASE STUDY 2: MEDIAN FILTER USING AN IMAGE PROCESSING LI
BRARY 769
10.3.1 THE MEDIAN FILTER 770
10.3.2 MEDIAN FILTER IN HDL 772
10.3.3 NIOS MEDIAN FILTERING IMAGE PROCESSING SYSTEM 775
10.3.4 MEDIAN FILTER IN SW 777
10.4 MOTION DETECTION 782
10.4.1 MOTION DETECTION 782
10.4.2 ME CO-PROCESSOR DESIGN 785
10.4.3 VIDEO COMPRESSION STANDARDS 788
EXERCISES 791
APPENDIX A. VERILOG CODE OF DESIGN EXAMPLES 795
CONTENTS XXIII
APPENDIX B. DESIGN EXAMPLES SYNTHESIS RESULTS 879
APPENDIX C. VHDL AND VERILOG CODING KEYWORDS 883
APPENDIX D. CD-ROM CONTENT 885
APPENDIX E. GLOSSARY 895
REFERENCES 903
INDEX 923 |
| any_adam_object | 1 |
| author | Meyer-Baese, Uwe 1964- |
| author_GND | (DE-588)14179514X |
| author_facet | Meyer-Baese, Uwe 1964- |
| author_role | aut |
| author_sort | Meyer-Baese, Uwe 1964- |
| author_variant | u m b umb |
| building | Verbundindex |
| bvnumber | BV042014484 |
| classification_rvk | ZN 4904 ZN 6040 |
| ctrlnum | (OCoLC)865147334 (DE-599)DNB1044794844 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 4th ed. |
| format | Book |
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| indexdate | 2024-09-10T01:20:48Z |
| institution | BVB |
| isbn | 9783642453083 9783642453090 3642453082 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027456307 |
| oclc_num | 865147334 |
| open_access_boolean | |
| owner | DE-83 DE-523 |
| owner_facet | DE-83 DE-523 |
| physical | XXIII, 930 S. Ill., graph. Darst. 1 CD-ROM |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| publisher | Springer |
| record_format | marc |
| series2 | Signals and communication technology |
| spelling | Meyer-Baese, Uwe 1964- Verfasser (DE-588)14179514X aut Digital signal processing with field programmable gate arrays Uwe Meyer-Baese 4th ed. Berlin [u.a.] Springer 2014 XXIII, 930 S. Ill., graph. Darst. 1 CD-ROM txt rdacontent n rdamedia nc rdacarrier Signals and communication technology Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Digitale Signalverarbeitung (DE-588)4113314-6 gnd rswk-swf (DE-588)4123623-3 Lehrbuch gnd-content Digitale Signalverarbeitung (DE-588)4113314-6 s Field programmable gate array (DE-588)4347749-5 s DE-604 Erscheint auch als Online-Ausgabe Digital Signal Processing with Field Programmable Gate Arrays X:MVB text/html http://deposit.dnb.de/cgi-bin/dokserv?id=4528645&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027456307&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Meyer-Baese, Uwe 1964- Digital signal processing with field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4113314-6 (DE-588)4123623-3 |
| title | Digital signal processing with field programmable gate arrays |
| title_auth | Digital signal processing with field programmable gate arrays |
| title_exact_search | Digital signal processing with field programmable gate arrays |
| title_full | Digital signal processing with field programmable gate arrays Uwe Meyer-Baese |
| title_fullStr | Digital signal processing with field programmable gate arrays Uwe Meyer-Baese |
| title_full_unstemmed | Digital signal processing with field programmable gate arrays Uwe Meyer-Baese |
| title_short | Digital signal processing with field programmable gate arrays |
| title_sort | digital signal processing with field programmable gate arrays |
| topic | Field programmable gate array (DE-588)4347749-5 gnd Digitale Signalverarbeitung (DE-588)4113314-6 gnd |
| topic_facet | Field programmable gate array Digitale Signalverarbeitung Lehrbuch |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=4528645&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027456307&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT meyerbaeseuwe digitalsignalprocessingwithfieldprogrammablegatearrays |