Digital design: with a introduction to the Verilog HDL
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Upper Saddle River, NJ [u.a.]
Pearson
2013
|
| Edition: | 5th ed, intern. ed. |
| Series: | Always learning
|
| Subjects: | |
| Physical Description: | 563 S. graph. Darst. |
| ISBN: | 9780273764526 |
Staff View
MARC
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| 245 | 1 | 0 | |a Digital design |b with a introduction to the Verilog HDL |c M. Morris Mano ; Michael D. Ciletti |
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Record in the Search Index
| _version_ | 1804152403604275200 |
|---|---|
| any_adam_object | |
| author | Mano, Moshe Morris 1927- Ciletti, Michael D. |
| author_GND | (DE-588)172248078 |
| author_facet | Mano, Moshe Morris 1927- Ciletti, Michael D. |
| author_role | aut aut |
| author_sort | Mano, Moshe Morris 1927- |
| author_variant | m m m mm mmm m d c md mdc |
| building | Verbundindex |
| bvnumber | BV041995689 |
| classification_rvk | ZN 4904 ZN 5620 |
| ctrlnum | (OCoLC)794166063 (DE-599)GBV690076754 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 5th ed, intern. ed. |
| format | Book |
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| id | DE-604.BV041995689 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T01:10:09Z |
| institution | BVB |
| isbn | 9780273764526 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027437840 |
| oclc_num | 794166063 |
| open_access_boolean | |
| owner | DE-83 DE-B768 |
| owner_facet | DE-83 DE-B768 |
| physical | 563 S. graph. Darst. |
| publishDate | 2013 |
| publishDateSearch | 2013 |
| publishDateSort | 2013 |
| publisher | Pearson |
| record_format | marc |
| series2 | Always learning |
| spelling | Mano, Moshe Morris 1927- Verfasser (DE-588)172248078 aut Digital design with a introduction to the Verilog HDL M. Morris Mano ; Michael D. Ciletti 5th ed, intern. ed. Upper Saddle River, NJ [u.a.] Pearson 2013 563 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Always learning Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 s Kundenspezifische Schaltung (DE-588)4122250-7 s Schaltungsentwurf (DE-588)4179389-4 s VHDL (DE-588)4254792-1 s VERILOG (DE-588)4268385-3 s DE-604 Ciletti, Michael D. Verfasser aut |
| spellingShingle | Mano, Moshe Morris 1927- Ciletti, Michael D. Digital design with a introduction to the Verilog HDL Digitale integrierte Schaltung (DE-588)4113313-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Schaltungsentwurf (DE-588)4179389-4 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4113313-4 (DE-588)4122250-7 (DE-588)4179389-4 (DE-588)4268385-3 (DE-588)4254792-1 |
| title | Digital design with a introduction to the Verilog HDL |
| title_auth | Digital design with a introduction to the Verilog HDL |
| title_exact_search | Digital design with a introduction to the Verilog HDL |
| title_full | Digital design with a introduction to the Verilog HDL M. Morris Mano ; Michael D. Ciletti |
| title_fullStr | Digital design with a introduction to the Verilog HDL M. Morris Mano ; Michael D. Ciletti |
| title_full_unstemmed | Digital design with a introduction to the Verilog HDL M. Morris Mano ; Michael D. Ciletti |
| title_short | Digital design |
| title_sort | digital design with a introduction to the verilog hdl |
| title_sub | with a introduction to the Verilog HDL |
| topic | Digitale integrierte Schaltung (DE-588)4113313-4 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Schaltungsentwurf (DE-588)4179389-4 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Digitale integrierte Schaltung Kundenspezifische Schaltung Schaltungsentwurf VERILOG VHDL |
| work_keys_str_mv | AT manomoshemorris digitaldesignwithaintroductiontotheveriloghdl AT cilettimichaeld digitaldesignwithaintroductiontotheveriloghdl |