Planar Double-Gate Transistor: From Technology to Circuit
Gespeichert in:
1. Verfasser: | |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Dordrecht
Springer Netherlands
2009
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Schlagworte: | |
Online-Zugang: | BTU01 FHN01 FHR01 Volltext |
Beschreibung: | This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates |
Beschreibung: | 1 Online-Ressource |
ISBN: | 9781402093418 |
DOI: | 10.1007/978-1-4020-9341-8 |
Internformat
MARC
LEADER | 00000nmm a2200000zc 4500 | ||
---|---|---|---|
001 | BV041889558 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 140603s2009 |||| o||u| ||||||eng d | ||
020 | |a 9781402093418 |c Online |9 978-1-4020-9341-8 | ||
024 | 7 | |a 10.1007/978-1-4020-9341-8 |2 doi | |
035 | |a (OCoLC)698911128 | ||
035 | |a (DE-599)BVBBV041889558 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-634 |a DE-898 |a DE-92 |a DE-83 | ||
082 | 0 | |a 621.3815 |2 23 | |
084 | |a ZN 4960 |0 (DE-625)157426: |2 rvk | ||
100 | 1 | |a Amara, Amara |e Verfasser |4 aut | |
245 | 1 | 0 | |a Planar Double-Gate Transistor |b From Technology to Circuit |c edited by Amara Amara, Olivier Rozeau |
264 | 1 | |a Dordrecht |b Springer Netherlands |c 2009 | |
300 | |a 1 Online-Ressource | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
500 | |a This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates | ||
505 | 0 | |a Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design | |
650 | 4 | |a Engineering | |
650 | 4 | |a Particles (Nuclear physics) | |
650 | 4 | |a Systems engineering | |
650 | 4 | |a Optical materials | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Solid State Physics and Spectroscopy | |
650 | 4 | |a Optical and Electronic Materials | |
650 | 4 | |a Ingenieurwissenschaften | |
650 | 0 | 7 | |a Analoge integrierte Schaltung |0 (DE-588)4112519-8 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a MOS-FET |0 (DE-588)4207266-9 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Planartransistor |0 (DE-588)4174786-0 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a Planartransistor |0 (DE-588)4174786-0 |D s |
689 | 0 | 1 | |a MOS-FET |0 (DE-588)4207266-9 |D s |
689 | 0 | 2 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |D s |
689 | 0 | 3 | |a Analoge integrierte Schaltung |0 (DE-588)4112519-8 |D s |
689 | 0 | 4 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
700 | 1 | |a Rozeau, Olivier |e Sonstige |4 oth | |
776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-1-4020-9327-2 |
856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4020-9341-8 |x Verlag |3 Volltext |
912 | |a ZDB-2-ENG | ||
999 | |a oai:aleph.bib-bvb.de:BVB01-027333511 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u https://doi.org/10.1007/978-1-4020-9341-8 |l BTU01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
966 | e | |u https://doi.org/10.1007/978-1-4020-9341-8 |l FHN01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
966 | e | |u https://doi.org/10.1007/978-1-4020-9341-8 |l FHR01 |p ZDB-2-ENG |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804152238514372608 |
---|---|
any_adam_object | |
author | Amara, Amara |
author_facet | Amara, Amara |
author_role | aut |
author_sort | Amara, Amara |
author_variant | a a aa |
building | Verbundindex |
bvnumber | BV041889558 |
classification_rvk | ZN 4960 |
collection | ZDB-2-ENG |
contents | Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design |
ctrlnum | (OCoLC)698911128 (DE-599)BVBBV041889558 |
dewey-full | 621.3815 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.3815 |
dewey-search | 621.3815 |
dewey-sort | 3621.3815 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/978-1-4020-9341-8 |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04012nmm a2200637zc 4500</leader><controlfield tag="001">BV041889558</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">140603s2009 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781402093418</subfield><subfield code="c">Online</subfield><subfield code="9">978-1-4020-9341-8</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4020-9341-8</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)698911128</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV041889558</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4960</subfield><subfield code="0">(DE-625)157426:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Amara, Amara</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Planar Double-Gate Transistor</subfield><subfield code="b">From Technology to Circuit</subfield><subfield code="c">edited by Amara Amara, Olivier Rozeau</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Dordrecht</subfield><subfield code="b">Springer Netherlands</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Particles (Nuclear physics)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systems engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Optical materials</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Solid State Physics and Spectroscopy</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Optical and Electronic Materials</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ingenieurwissenschaften</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Analoge integrierte Schaltung</subfield><subfield code="0">(DE-588)4112519-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">MOS-FET</subfield><subfield code="0">(DE-588)4207266-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Planartransistor</subfield><subfield code="0">(DE-588)4174786-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Planartransistor</subfield><subfield code="0">(DE-588)4174786-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">MOS-FET</subfield><subfield code="0">(DE-588)4207266-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="3"><subfield code="a">Analoge integrierte Schaltung</subfield><subfield code="0">(DE-588)4112519-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="4"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Rozeau, Olivier</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-1-4020-9327-2</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4020-9341-8</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027333511</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-9341-8</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-9341-8</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-9341-8</subfield><subfield code="l">FHR01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV041889558 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T01:07:32Z |
institution | BVB |
isbn | 9781402093418 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027333511 |
oclc_num | 698911128 |
open_access_boolean | |
owner | DE-634 DE-898 DE-BY-UBR DE-92 DE-83 |
owner_facet | DE-634 DE-898 DE-BY-UBR DE-92 DE-83 |
physical | 1 Online-Ressource |
psigel | ZDB-2-ENG |
publishDate | 2009 |
publishDateSearch | 2009 |
publishDateSort | 2009 |
publisher | Springer Netherlands |
record_format | marc |
spelling | Amara, Amara Verfasser aut Planar Double-Gate Transistor From Technology to Circuit edited by Amara Amara, Olivier Rozeau Dordrecht Springer Netherlands 2009 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design Engineering Particles (Nuclear physics) Systems engineering Optical materials Circuits and Systems Solid State Physics and Spectroscopy Optical and Electronic Materials Ingenieurwissenschaften Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf MOS-FET (DE-588)4207266-9 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Planartransistor (DE-588)4174786-0 gnd rswk-swf Planartransistor (DE-588)4174786-0 s MOS-FET (DE-588)4207266-9 s CMOS-Schaltung (DE-588)4148111-2 s Analoge integrierte Schaltung (DE-588)4112519-8 s Digitale integrierte Schaltung (DE-588)4113313-4 s 1\p DE-604 Rozeau, Olivier Sonstige oth Erscheint auch als Druckausgabe 978-1-4020-9327-2 https://doi.org/10.1007/978-1-4020-9341-8 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Amara, Amara Planar Double-Gate Transistor From Technology to Circuit Multiple Gate Technologies -- Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach -- Compact Modeling of Double Gate MOSFET for IC Design -- Low Frequency Noise in Double-Gate SOI CMOS Devices -- Analog Circuit Design -- Logic Circuit Design with DGMOS Devices -- SRAM Circuit Design Engineering Particles (Nuclear physics) Systems engineering Optical materials Circuits and Systems Solid State Physics and Spectroscopy Optical and Electronic Materials Ingenieurwissenschaften Analoge integrierte Schaltung (DE-588)4112519-8 gnd CMOS-Schaltung (DE-588)4148111-2 gnd MOS-FET (DE-588)4207266-9 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd Planartransistor (DE-588)4174786-0 gnd |
subject_GND | (DE-588)4112519-8 (DE-588)4148111-2 (DE-588)4207266-9 (DE-588)4113313-4 (DE-588)4174786-0 |
title | Planar Double-Gate Transistor From Technology to Circuit |
title_auth | Planar Double-Gate Transistor From Technology to Circuit |
title_exact_search | Planar Double-Gate Transistor From Technology to Circuit |
title_full | Planar Double-Gate Transistor From Technology to Circuit edited by Amara Amara, Olivier Rozeau |
title_fullStr | Planar Double-Gate Transistor From Technology to Circuit edited by Amara Amara, Olivier Rozeau |
title_full_unstemmed | Planar Double-Gate Transistor From Technology to Circuit edited by Amara Amara, Olivier Rozeau |
title_short | Planar Double-Gate Transistor |
title_sort | planar double gate transistor from technology to circuit |
title_sub | From Technology to Circuit |
topic | Engineering Particles (Nuclear physics) Systems engineering Optical materials Circuits and Systems Solid State Physics and Spectroscopy Optical and Electronic Materials Ingenieurwissenschaften Analoge integrierte Schaltung (DE-588)4112519-8 gnd CMOS-Schaltung (DE-588)4148111-2 gnd MOS-FET (DE-588)4207266-9 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd Planartransistor (DE-588)4174786-0 gnd |
topic_facet | Engineering Particles (Nuclear physics) Systems engineering Optical materials Circuits and Systems Solid State Physics and Spectroscopy Optical and Electronic Materials Ingenieurwissenschaften Analoge integrierte Schaltung CMOS-Schaltung MOS-FET Digitale integrierte Schaltung Planartransistor |
url | https://doi.org/10.1007/978-1-4020-9341-8 |
work_keys_str_mv | AT amaraamara planardoublegatetransistorfromtechnologytocircuit AT rozeauolivier planardoublegatetransistorfromtechnologytocircuit |