Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Dordrecht
Springer Netherlands
2009
|
| Subjects: | |
| Online Access: | BTU01 FHN01 FHR01 Volltext |
| Item Description: | Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of - High-Speed Clock and Data Recovery - Chaired by Prof. M. Steyaert, Catholic University Leuven - High-Performance Amplifiers - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology - Power Management - Chaired by Herman Casier, AMI Semiconductor Fellow Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design |
| Physical Description: | 1 Online-Ressource |
| ISBN: | 9781402089442 |
| DOI: | 10.1007/978-1-4020-8944-2 |
Staff View
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV041889553 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 140603s2009 |||| o||u| ||||||eng d | ||
| 020 | |a 9781402089442 |c Online |9 978-1-4020-8944-2 | ||
| 024 | 7 | |a 10.1007/978-1-4020-8944-2 |2 doi | |
| 035 | |a (OCoLC)881615324 | ||
| 035 | |a (DE-599)BVBBV041889553 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 |a DE-898 |a DE-92 |a DE-83 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 084 | |a ZN 5530 |0 (DE-625)157465: |2 rvk | ||
| 100 | 1 | |a Steyaert, Michiel |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Analog Circuit Design |b High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management |c edited by Michiel Steyaert, Arthur H. M. van Roermund, Herman Casier |
| 264 | 1 | |a Dordrecht |b Springer Netherlands |c 2009 | |
| 300 | |a 1 Online-Ressource | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of - High-Speed Clock and Data Recovery - Chaired by Prof. M. Steyaert, Catholic University Leuven - High-Performance Amplifiers - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology - Power Management - Chaired by Herman Casier, AMI Semiconductor Fellow Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design | ||
| 505 | 0 | |a High-Speed Clock and Data Recovery -- Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial -- Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links -- Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes Developments in nm Technologies -- Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits -- Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes -- Time to Digital Conversion: An Alternative View on Synchronization -- High-Performance Amplifiers -- Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers -- Current Sense Amplifiers with Extended Common Mode Voltage Range -- Low-Voltage Power-Efficient Amplifiers for Emerging Applications -- Integrated Amplifier Architectures for Efficient Coupling to the Nervous System -- Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices -- Design of High Power Class-D Audio Amplifiers -- Power Management -- Single-Inductor Multiple-Output Dc-Dc Converters -- Enhanced Ripple Regulators -- Robust DCDC Converter for Automotive Applications -- Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies -- Wideband Efficient Amplifiers for On-Chip Adaptive Power Management Applications -- Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer science | |
| 650 | 4 | |a Systems engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Processor Architectures | |
| 650 | 4 | |a Informatik | |
| 650 | 4 | |a Ingenieurwissenschaften | |
| 650 | 0 | 7 | |a Analogschaltung |0 (DE-588)4122796-7 |2 gnd |9 rswk-swf |
| 651 | 7 | |a Pavia |0 (DE-588)4044970-1 |2 gnd |9 rswk-swf | |
| 655 | 7 | |8 1\p |0 (DE-588)1071861417 |a Konferenzschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Analogschaltung |0 (DE-588)4122796-7 |D s |
| 689 | 0 | 1 | |a Pavia |0 (DE-588)4044970-1 |D g |
| 689 | 0 | |8 2\p |5 DE-604 | |
| 700 | 1 | |a Roermund, Arthur H. M. van |e Sonstige |4 oth | |
| 700 | 1 | |a Casier, Herman |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-1-4020-8943-5 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4020-8944-2 |x Verlag |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027333506 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-1-4020-8944-2 |l BTU01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-1-4020-8944-2 |l FHN01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-1-4020-8944-2 |l FHR01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
Record in the Search Index
| _version_ | 1804152238485012480 |
|---|---|
| any_adam_object | |
| author | Steyaert, Michiel |
| author_facet | Steyaert, Michiel |
| author_role | aut |
| author_sort | Steyaert, Michiel |
| author_variant | m s ms |
| building | Verbundindex |
| bvnumber | BV041889553 |
| classification_rvk | ZN 5530 |
| collection | ZDB-2-ENG |
| contents | High-Speed Clock and Data Recovery -- Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial -- Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links -- Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes Developments in nm Technologies -- Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits -- Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes -- Time to Digital Conversion: An Alternative View on Synchronization -- High-Performance Amplifiers -- Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers -- Current Sense Amplifiers with Extended Common Mode Voltage Range -- Low-Voltage Power-Efficient Amplifiers for Emerging Applications -- Integrated Amplifier Architectures for Efficient Coupling to the Nervous System -- Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices -- Design of High Power Class-D Audio Amplifiers -- Power Management -- Single-Inductor Multiple-Output Dc-Dc Converters -- Enhanced Ripple Regulators -- Robust DCDC Converter for Automotive Applications -- Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies -- Wideband Efficient Amplifiers for On-Chip Adaptive Power Management Applications -- Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise |
| ctrlnum | (OCoLC)881615324 (DE-599)BVBBV041889553 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4020-8944-2 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04807nmm a2200589zc 4500</leader><controlfield tag="001">BV041889553</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">140603s2009 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781402089442</subfield><subfield code="c">Online</subfield><subfield code="9">978-1-4020-8944-2</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4020-8944-2</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)881615324</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV041889553</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5530</subfield><subfield code="0">(DE-625)157465:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Steyaert, Michiel</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Analog Circuit Design</subfield><subfield code="b">High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management</subfield><subfield code="c">edited by Michiel Steyaert, Arthur H. M. van Roermund, Herman Casier</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Dordrecht</subfield><subfield code="b">Springer Netherlands</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of - High-Speed Clock and Data Recovery - Chaired by Prof. M. Steyaert, Catholic University Leuven - High-Performance Amplifiers - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology - Power Management - Chaired by Herman Casier, AMI Semiconductor Fellow Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">High-Speed Clock and Data Recovery -- Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial -- Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links -- Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes Developments in nm Technologies -- Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits -- Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes -- Time to Digital Conversion: An Alternative View on Synchronization -- High-Performance Amplifiers -- Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers -- Current Sense Amplifiers with Extended Common Mode Voltage Range -- Low-Voltage Power-Efficient Amplifiers for Emerging Applications -- Integrated Amplifier Architectures for Efficient Coupling to the Nervous System -- Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices -- Design of High Power Class-D Audio Amplifiers -- Power Management -- Single-Inductor Multiple-Output Dc-Dc Converters -- Enhanced Ripple Regulators -- Robust DCDC Converter for Automotive Applications -- Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies -- Wideband Efficient Amplifiers for On-Chip Adaptive Power Management Applications -- Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer science</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systems engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Processor Architectures</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Informatik</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ingenieurwissenschaften</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Analogschaltung</subfield><subfield code="0">(DE-588)4122796-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="651" ind1=" " ind2="7"><subfield code="a">Pavia</subfield><subfield code="0">(DE-588)4044970-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="8">1\p</subfield><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Analogschaltung</subfield><subfield code="0">(DE-588)4122796-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Pavia</subfield><subfield code="0">(DE-588)4044970-1</subfield><subfield code="D">g</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Roermund, Arthur H. M. van</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Casier, Herman</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-1-4020-8943-5</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4020-8944-2</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027333506</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-8944-2</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-8944-2</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4020-8944-2</subfield><subfield code="l">FHR01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| genre | 1\p (DE-588)1071861417 Konferenzschrift gnd-content |
| genre_facet | Konferenzschrift |
| geographic | Pavia (DE-588)4044970-1 gnd |
| geographic_facet | Pavia |
| id | DE-604.BV041889553 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:07:32Z |
| institution | BVB |
| isbn | 9781402089442 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027333506 |
| oclc_num | 881615324 |
| open_access_boolean | |
| owner | DE-634 DE-898 DE-BY-UBR DE-92 DE-83 |
| owner_facet | DE-634 DE-898 DE-BY-UBR DE-92 DE-83 |
| physical | 1 Online-Ressource |
| psigel | ZDB-2-ENG |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Springer Netherlands |
| record_format | marc |
| spelling | Steyaert, Michiel Verfasser aut Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management edited by Michiel Steyaert, Arthur H. M. van Roermund, Herman Casier Dordrecht Springer Netherlands 2009 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of - High-Speed Clock and Data Recovery - Chaired by Prof. M. Steyaert, Catholic University Leuven - High-Performance Amplifiers - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology - Power Management - Chaired by Herman Casier, AMI Semiconductor Fellow Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design High-Speed Clock and Data Recovery -- Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial -- Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links -- Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes Developments in nm Technologies -- Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits -- Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes -- Time to Digital Conversion: An Alternative View on Synchronization -- High-Performance Amplifiers -- Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers -- Current Sense Amplifiers with Extended Common Mode Voltage Range -- Low-Voltage Power-Efficient Amplifiers for Emerging Applications -- Integrated Amplifier Architectures for Efficient Coupling to the Nervous System -- Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices -- Design of High Power Class-D Audio Amplifiers -- Power Management -- Single-Inductor Multiple-Output Dc-Dc Converters -- Enhanced Ripple Regulators -- Robust DCDC Converter for Automotive Applications -- Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies -- Wideband Efficient Amplifiers for On-Chip Adaptive Power Management Applications -- Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Informatik Ingenieurwissenschaften Analogschaltung (DE-588)4122796-7 gnd rswk-swf Pavia (DE-588)4044970-1 gnd rswk-swf 1\p (DE-588)1071861417 Konferenzschrift gnd-content Analogschaltung (DE-588)4122796-7 s Pavia (DE-588)4044970-1 g 2\p DE-604 Roermund, Arthur H. M. van Sonstige oth Casier, Herman Sonstige oth Erscheint auch als Druckausgabe 978-1-4020-8943-5 https://doi.org/10.1007/978-1-4020-8944-2 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Steyaert, Michiel Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management High-Speed Clock and Data Recovery -- Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial -- Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links -- Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes Developments in nm Technologies -- Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits -- Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes -- Time to Digital Conversion: An Alternative View on Synchronization -- High-Performance Amplifiers -- Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers -- Current Sense Amplifiers with Extended Common Mode Voltage Range -- Low-Voltage Power-Efficient Amplifiers for Emerging Applications -- Integrated Amplifier Architectures for Efficient Coupling to the Nervous System -- Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices -- Design of High Power Class-D Audio Amplifiers -- Power Management -- Single-Inductor Multiple-Output Dc-Dc Converters -- Enhanced Ripple Regulators -- Robust DCDC Converter for Automotive Applications -- Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies -- Wideband Efficient Amplifiers for On-Chip Adaptive Power Management Applications -- Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Informatik Ingenieurwissenschaften Analogschaltung (DE-588)4122796-7 gnd |
| subject_GND | (DE-588)4122796-7 (DE-588)4044970-1 (DE-588)1071861417 |
| title | Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management |
| title_auth | Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management |
| title_exact_search | Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management |
| title_full | Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management edited by Michiel Steyaert, Arthur H. M. van Roermund, Herman Casier |
| title_fullStr | Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management edited by Michiel Steyaert, Arthur H. M. van Roermund, Herman Casier |
| title_full_unstemmed | Analog Circuit Design High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management edited by Michiel Steyaert, Arthur H. M. van Roermund, Herman Casier |
| title_short | Analog Circuit Design |
| title_sort | analog circuit design high speed clock and data recovery high performance amplifiers power management |
| title_sub | High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management |
| topic | Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Informatik Ingenieurwissenschaften Analogschaltung (DE-588)4122796-7 gnd |
| topic_facet | Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Informatik Ingenieurwissenschaften Analogschaltung Pavia Konferenzschrift |
| url | https://doi.org/10.1007/978-1-4020-8944-2 |
| work_keys_str_mv | AT steyaertmichiel analogcircuitdesignhighspeedclockanddatarecoveryhighperformanceamplifierspowermanagement AT roermundarthurhmvan analogcircuitdesignhighspeedclockanddatarecoveryhighperformanceamplifierspowermanagement AT casierherman analogcircuitdesignhighspeedclockanddatarecoveryhighperformanceamplifierspowermanagement |