Enabling functional tests of asynchronous circuits using a test processor solution:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
2013
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| Schlagworte: | |
| Online-Zugang: | kostenfrei Inhaltsverzeichnis |
| Beschreibung: | XI, 214 S. graph. Darst. |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1804151863364288512 |
|---|---|
| adam_text | CONTENTS
CONTENTS I
ABSTRACT VII
ZUSAMMENFASSUNG VIII
1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 CONTRIBUTION TO THE STATE-OF-THE-ART 2
1.3 PUBLICATIONS RELATED TO THIS WORK 5
1.4 OVERVIEW OF THE WORK 5
2 BASICS OF ASYNCHRONOUS CIRCUITS AND THEIR TESTING 7
2.1 ASYNCHRONOUS CIRCUITS 7
2.1.1 CONCEPT AND HISTORY 7
2.1.2 SYNCHRONOUS VERSUS ASYNCHRONOUS DESIGNS 9
2.1.3 ASYNCHRONOUS HANDSHAKE PROTOCOLS 11
2.1.4 ASYNCHRONOUS CHANNELS 16
2.1.5 CLASSIFICATION BASED ON DELAY MODELS 16
2.1.6 ELEMENTARY COMPONENTS 17
2.1.7 DESIGN ISSUES OF ASYNCHRONOUS CIRCUITS 19
2.1.8 MODELLING AND DESIGN OF ASYNCHRONOUS CIRCUITS 23
2.1.9 TYPICAL ARCHITECTURES OF ASYNCHRONOUS CIRCUITS 27
2.2 TESTING OF ASYNCHRONOUS CIRCUITS 35
2.2.1 FAULT MODELS 35
2.2.2 STANDARD TEST METHODS 37
3 THE CHALLENGE OF FUNCTIONAL TESTS OF ASYNCHRONOUS DESIGNS 43
I
HTTP://D-NB.INFO/1049220072
11
CONTENTS
3.1 DISCUSSION OF THE PROBLEM 43
3.2 ALTERNATIVE SOLUTIONS 45
3.2.1 ASSUMING WORST-CASE BEHAVIOR 45
3.2.2 UTILIZATION OF SCAN 46
3.2.3 UTILIZATION OF BUILT-IN SELF-TEST 47
3.2.4 UTILIZATION OF MEMORIES AND FIFOS 48
3.2.5 ELIMINATING NON-DETERMINISTIC BEHAVIOR 49
4 CONCEPT FOR FUNCTIONAL TESTS OF ASYNCHRONOUS CIRCUITS 51
4.1 MODEL OF THE DEVICE-UNDER-TEST 51
4.2 TEST PROCESSOR CONCEPT 52
4.2.1 IMPLEMENTATION SCHEMES 54
4.2.2 DEFINITION OF INTERFACES 56
4.2.3 ROLE OF THE PROCESSOR CORE 58
4.3 WORKFLOW 59
4.3.1 EMBEDDING THE DUT INTO THE TEST PROCESSOR INFRASTRUCTURE ... 59
4.3.2 GENERATION OF TESTS : 61
4.4 SUMMARY OF THE CONCEPT 73
5 TEST PROCESSOR IMPLEMENTATION 75
5.1 DESIGN DECISIONS 75
5.2 HARDWARE IMPLEMENTATION 78
5.2.1 GLOBAL ARCHITECTURE OF NOTEPAD 78
5.2.2 DESIGN OF THE DATA PORTS 80
5.2.3 DESIGN OF THE HANDSHAKE PORTS 89
5.2.4 DESIGN OF THE PORT SWITCH 93
5.2.5 ARCHITECTURE OF THE MEMORY ACCESS CONTROLLER 96
5.2.6 ARCHITECTURE OF THE SEQUENCER 99
5.3 INSTRUCTION SET 103
5.4 TOOLS RELATED TO THE PROCESSOR 108
6 TEST PROGRAM GENERATION 109
6.1 THE CHANNEL SIMULATION PACKAGE 109
6.1.1 PRECONSIDERATIONS 110
6.1.2 TEST PROCESSOR AND PACKAGE SETUP ILL
6.1.3 PROCEDURES FOR ACCESSING THE TRANSFER PROTOCOL 112
6.1.4 MODEL OF THE HANDSHAKE PROTOCOL TYPE 113
6.1.5 CHANNEL RESOURCES 114
CONTENTS III
6.1.6 SIGNAL RESOURCES 117
6.1.7 MISCELLANEOUS FUNCTIONS 120
6.1.8 IMPLEMENTATION OF THE SEQUENCE GENERATION ALGORITHM 120
6.2 MAPPING OF A TRANSFER PROTOCOL TO A PROCESSOR PROGRAM 130
6.2.1 PRECONSIDERATIONS REGARDING THE PROGRAM GENERATION 130
6.2.2 MAPPING TO NOTEPAD INSTRUCTIONS 134
6.2.3 COMPILER FOR GENERATING TEST PROGRAMS FROM TRANSFER PROTOCOLS 145
7 EVALUATION OF THE CONCEPT 147
7.1 APPLICATION OF THE FRAMEWORK TO AN ASYNCHRONOUS DEVICE 147
7.1.1 THE DEVICE-UNDER-TEST 148
7.1.2 DEMONSTRATOR 150
7.1.3 TEST PROGRAM GENERATION 151
7.1.4 TEST RESULTS AND FURTHER OPTIMIZATIONS OF THE GENERATED PROGRAM
156
7.2 EVALUATION OF THE PROCESSOR IMPLEMENTATION 159
7.2.1 HARDWARE REQUIREMENTS OF THE FPGA IMPLEMENTATION 159
7.2.2 TEST EXECUTION PROPERTIES 161
7.3 A TEST SCENARIO 165
8 CONCLUSIONS 167
8.1 SUMMARY OF THE WORK 167
8.2 SUMMARY OF THE ACHIEVEMENTS 169
8.3 IMPACT OF THE SOLUTION 169
8.4 LIMITATIONS OF THE APPROACH 170
8.5 OUTLOOK ON FUTURE ACTIVITIES 170
A HANDSHAKE PROTOCOL IMPLEMENTATIONS 173
B PROTOCOL CONVERTERS 177
C TOOLS 179
C.L TRANSFER PROTOCOL COMPILER 179
C.2 MEMORY MAP CONVERTER 181
D DEMONSTRATOR 183
LIST OF FIGURES 195
LIST OF TABLES 198
LISTINGS
BIBLIOGRAPHY
|
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| spelling | Zeidler, Steffen Verfasser aut Enabling functional tests of asynchronous circuits using a test processor solution Steffen Zeidler 2013 XI, 214 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Cottbus-Senftenberg, Techn. Univ., Diss., 2013 Asynchrones Schaltwerk (DE-588)4271581-7 gnd rswk-swf Prüftechnik (DE-588)4047610-8 gnd rswk-swf Fehlererkennung (DE-588)4133764-5 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Asynchrones Schaltwerk (DE-588)4271581-7 s Prüftechnik (DE-588)4047610-8 s Fehlererkennung (DE-588)4133764-5 s DE-604 Erscheint auch als Online-Ausgabe urn:nbn:de:kobv:co1-opus-29643 http://opus.kobv.de/btu/volltexte/2014/2964/ kostenfrei Volltext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027081553&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Zeidler, Steffen Enabling functional tests of asynchronous circuits using a test processor solution Asynchrones Schaltwerk (DE-588)4271581-7 gnd Prüftechnik (DE-588)4047610-8 gnd Fehlererkennung (DE-588)4133764-5 gnd |
| subject_GND | (DE-588)4271581-7 (DE-588)4047610-8 (DE-588)4133764-5 (DE-588)4113937-9 |
| title | Enabling functional tests of asynchronous circuits using a test processor solution |
| title_auth | Enabling functional tests of asynchronous circuits using a test processor solution |
| title_exact_search | Enabling functional tests of asynchronous circuits using a test processor solution |
| title_full | Enabling functional tests of asynchronous circuits using a test processor solution Steffen Zeidler |
| title_fullStr | Enabling functional tests of asynchronous circuits using a test processor solution Steffen Zeidler |
| title_full_unstemmed | Enabling functional tests of asynchronous circuits using a test processor solution Steffen Zeidler |
| title_short | Enabling functional tests of asynchronous circuits using a test processor solution |
| title_sort | enabling functional tests of asynchronous circuits using a test processor solution |
| topic | Asynchrones Schaltwerk (DE-588)4271581-7 gnd Prüftechnik (DE-588)4047610-8 gnd Fehlererkennung (DE-588)4133764-5 gnd |
| topic_facet | Asynchrones Schaltwerk Prüftechnik Fehlererkennung Hochschulschrift |
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