Turbo Decoder Architecture for Beyond-4G Applications:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2014
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| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext |
| Beschreibung: | This book describes the most recent techniques for turbo decoder implementation, especially for 4G and beyond 4G applications. The authors reveal techniques for the design of high-throughput decoders for future telecommunication systems, enabling designers to reduce hardware cost and shorten processing time. Coverage includes an explanation of VLSI implementation of the turbo decoder, from basic functional units to advanced parallel architecture. Several state-of-the-art techniques that improve complexity and/or throughput are introduced. The authors discuss both hardware architecture techniques and experimental results, showing the variations in area/throughput/performance with respect to several techniques. This book also illustrates turbo decoders for 3GPP-LTE/LTE-A and IEEE 802.16e/m standards, which provide a low-complexity but high-flexibility circuit structure to support these standards and enables designs that reconfigure block size and parallelism. Case studies include the discussions of both throughput and performance of each mode (block size/parallelism/iteration). This book not only highlights the critical design issues that restrict the speedup of parallel architecture, but it also provides the solutions to overcome these limitations by modifying slightly the turbo codec of modern standards. · Offers readers a complete introduction to practical turbo decoder design; · Describes different design methodologies and explains the trade-offs between performance improvement and overhead; · Explains modern techniques for state-of-the-art designs; · Includes simulation and implementation results with respect to various decoder circuit designs; · Reveals novel approaches to higher operating efficiency of turbo decoders for beyond 4G applications |
| Beschreibung: | 1 Online-Ressource (VIII, 100 p.) 36 illus., 3 illus. in color |
| ISBN: | 9781461483106 |
| DOI: | 10.1007/978-1-4614-8310-6 |
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| 505 | 0 | |a Introduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture | |
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| 650 | 4 | |a Processor Architectures | |
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Datensatz im Suchindex
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| author | Wong, Cheng-Chi |
| author_facet | Wong, Cheng-Chi |
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| bvnumber | BV041470889 |
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| contents | Introduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture |
| ctrlnum | (OCoLC)865039307 (DE-599)BVBBV041470889 |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4614-8310-6 |
| format | Electronic eBook |
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| id | DE-604.BV041470889 |
| illustrated | Illustrated |
| indexdate | 2025-02-20T06:39:06Z |
| institution | BVB |
| isbn | 9781461483106 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-026917031 |
| oclc_num | 865039307 |
| open_access_boolean | |
| owner | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| owner_facet | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource (VIII, 100 p.) 36 illus., 3 illus. in color |
| psigel | ZDB-2-ENG |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| record_format | marc |
| spellingShingle | Wong, Cheng-Chi Turbo Decoder Architecture for Beyond-4G Applications Introduction -- Conventional Architecture of Turbo Decoder -- Turbo Decoder with Parallel Processing -- Low-Complexity Solution for Highly Parallel Architecture -- High Efficiency Solution for Highly Parallel Architecture Engineering Computer science Telecommunication Systems engineering Circuits and Systems Communications Engineering, Networks Processor Architectures Informatik Ingenieurwissenschaften |
| title | Turbo Decoder Architecture for Beyond-4G Applications |
| title_auth | Turbo Decoder Architecture for Beyond-4G Applications |
| title_exact_search | Turbo Decoder Architecture for Beyond-4G Applications |
| title_full | Turbo Decoder Architecture for Beyond-4G Applications by Cheng-Chi Wong, Hsie-Chia Chang |
| title_fullStr | Turbo Decoder Architecture for Beyond-4G Applications by Cheng-Chi Wong, Hsie-Chia Chang |
| title_full_unstemmed | Turbo Decoder Architecture for Beyond-4G Applications by Cheng-Chi Wong, Hsie-Chia Chang |
| title_short | Turbo Decoder Architecture for Beyond-4G Applications |
| title_sort | turbo decoder architecture for beyond 4g applications |
| topic | Engineering Computer science Telecommunication Systems engineering Circuits and Systems Communications Engineering, Networks Processor Architectures Informatik Ingenieurwissenschaften |
| topic_facet | Engineering Computer science Telecommunication Systems engineering Circuits and Systems Communications Engineering, Networks Processor Architectures Informatik Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-1-4614-8310-6 |
| work_keys_str_mv | AT wongchengchi turbodecoderarchitectureforbeyond4gapplications AT changhsiechia turbodecoderarchitectureforbeyond4gapplications |