High Performance Multi-Channel High-Speed I/O Circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2014
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| Schriftenreihe: | Analog Circuits and Signal Processing
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| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext |
| Beschreibung: | This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. · Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits; · Includes critical background knowledge related to channel ISI equalization circuits; · Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems |
| Beschreibung: | 1 Online-Ressource (X, 89 p.) 64 illus., 44 illus. in color |
| ISBN: | 9781461449638 |
| DOI: | 10.1007/978-1-4614-4963-8 |
Internformat
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| 500 | |a This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. · Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits; · Includes critical background knowledge related to channel ISI equalization circuits; · Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems | ||
| 505 | 0 | |a Introduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling | |
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| 650 | 4 | |a Microwaves, RF and Optical Engineering | |
| 650 | 4 | |a Ingenieurwissenschaften | |
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Datensatz im Suchindex
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| author | Oh, Taehyoun |
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| author_sort | Oh, Taehyoun |
| author_variant | t o to |
| building | Verbundindex |
| bvnumber | BV041470859 |
| collection | ZDB-2-ENG |
| contents | Introduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling |
| ctrlnum | (OCoLC)862985504 (DE-599)BVBBV041470859 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4614-4963-8 |
| format | Electronic eBook |
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| id | DE-604.BV041470859 |
| illustrated | Illustrated |
| indexdate | 2024-08-01T10:55:48Z |
| institution | BVB |
| isbn | 9781461449638 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-026917001 |
| oclc_num | 862985504 |
| open_access_boolean | |
| owner | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| owner_facet | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource (X, 89 p.) 64 illus., 44 illus. in color |
| psigel | ZDB-2-ENG |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| record_format | marc |
| series2 | Analog Circuits and Signal Processing |
| spellingShingle | Oh, Taehyoun High Performance Multi-Channel High-Speed I/O Circuits Introduction -- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process -- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process -- Adaptive XTCR, AGC, and Adaptive DFE Loop -- Research Summary & Contributions -- References -- Appendix A: Noise Analysis -- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4) -- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter -- Appendix D: Line Mismatch Sensitivity -- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench -- Appendix F: Bandwidth Improvement by Technology Scaling Engineering Microwaves Electronics Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Microwaves, RF and Optical Engineering Ingenieurwissenschaften |
| title | High Performance Multi-Channel High-Speed I/O Circuits |
| title_auth | High Performance Multi-Channel High-Speed I/O Circuits |
| title_exact_search | High Performance Multi-Channel High-Speed I/O Circuits |
| title_full | High Performance Multi-Channel High-Speed I/O Circuits by Taehyoun Oh, Ramesh Harjani |
| title_fullStr | High Performance Multi-Channel High-Speed I/O Circuits by Taehyoun Oh, Ramesh Harjani |
| title_full_unstemmed | High Performance Multi-Channel High-Speed I/O Circuits by Taehyoun Oh, Ramesh Harjani |
| title_short | High Performance Multi-Channel High-Speed I/O Circuits |
| title_sort | high performance multi channel high speed i o circuits |
| topic | Engineering Microwaves Electronics Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Microwaves, RF and Optical Engineering Ingenieurwissenschaften |
| topic_facet | Engineering Microwaves Electronics Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Microwaves, RF and Optical Engineering Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-1-4614-4963-8 |
| work_keys_str_mv | AT ohtaehyoun highperformancemultichannelhighspeediocircuits AT harjaniramesh highperformancemultichannelhighspeediocircuits |