Progress in VLSI design and test: 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings
Saved in:
| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Berlin [u.a.]
Springer
2012
|
| Series: | Lecture notes in computer science
7373 |
| Subjects: | |
| Online Access: | Inhaltstext Inhaltsverzeichnis |
| Physical Description: | XXII, 408 S. graph. Darst. |
| ISBN: | 3642314937 9783642314933 |
Staff View
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IMAGE 1
TABLE O F C O N T E N T S
LOWER P O W E R 1 AN EFFICIENT HIGH FREQUENCY AND LOW POWER ANALOG
MULTIPLIER IN CURRENT DOMAIN 1
A N U GUPTA AND SUBHROJYOTI SARKAR
DESIGN OF PUSH-PULL DYNAMIC LEAKER CIRCUIT FOR A LOW POWER EMBEDDED
VOLTAGE REGULATOR 10
BISWAJIT MAITY AND PRADIP MANDAL
POWER MODELING OF POWER GATED FSM AND ITS LOW POWER REALIZATION BY
SIMULTANEOUS PARTITIONING AND STATE ENCODING USING GENETIC ALGORITHM 19
PRIYANKA CHOUDHURY AND SAMBHU NATH PRADHAN
A N A L O G V L S I D E S I G N I
DESIGN AND IMPLEMENTATION OF A LINEAR FEEDBACK SHIFT REGISTER
INTERLEAVE!' FOR TURBO DECODING 30
RAHUL SHRESTHA AND ROY PAILY
LOW COMPLEXITY ENCODER FOR CROSSTALK REDUCTION IN R L C MODELED
INTERCONNECTS 40
GUNTI NAGENDRA BABU, BRAJESH K U M A R KAUSHIK, ANAND BULUSU, AND MANOJ
K U M A R MAJUMDER
ANALOG PERFORMANCE ANALYSIS OF DUAL-K SPACER BASED UNDERLAP F I N F E T
46
ASHUTOSH NANDI, ASHOK K. SAXENA, AND SUDEB DASGUPTA
T E S T A N D VERIFICATION I
IMPLEMENTATION OF GATING TECHNIQUE WITH MODIFIED SCAN FLIP-FLOP FOR LOW
POWER TESTING OF VLSI CHIPS 52
R. JAYAGOWRI AND K.S. GURUMURTHY
POST-BOND STACK TESTING FOR 3D STACKED IC 59
SURAJIT K U M A R ROY, DONA ROY, CHANDAN GIRI, AND HAFIZUR RAHAMAN
TRANSLATION VALIDATION FOR P R E S + MODELS OF PARALLEL BEHAVIOURS VIA
AN FSMD EQUIVALENCE CHECKER 69
SOUMYADIP BANDYOPADHYAY, KUNAL BANERJEE, DIPANKAR SARKAR, AND
CHITTARANJAN R. MANDAL
HTTP://D-NB.INFO/1023016354
IMAGE 2
XVIII TABLE OF CONTENTS
D E S I G N TECHNIQUES I
DESIGN OF HIGH SPEED VEDIC MULTIPLIER FOR DECIMAL NUMBER SYSTEM . . . .
79 PRABIR SAHA, ARINDAM BANERJEE, ANUP DANDAPAT, AND PARTHA
BHATTACHARYYA
AN EFFICIENT TEST DESIGN FOR CMPS CACHE COHERENCE REALIZING MESI
PROTOCOL 89
MAMATA DALUI AND BIPLAB K. SIKDAR
AN EFFICIENT HIGH SPEED IMPLEMENTATION OF FLEXIBLE CHARACTERISTIC-2
MULTIPLIERS ON F P G A S 99
DEBAPRIYA BASU ROY AND DEBDEEP MUKHOPADHYAY
A L G O R I T H M S A N D A P P L I C A T I O N S I
ARITHMETIC ALGORITHMS FOR TERNARY NUMBER SYSTEM SUBRATA DAS, PARTHA
SARATHI DASGUPTA, AND SAMAR SENSARMA
SOI MEMS BASED OVER-SAMPLING ACCELEROMETER DESIGN WITH A E O U T P U T
DUSHYANT JUNEJA, SOUGATA KAR, PROCHETA CHATTERJEE, AND SIDDHARTHA S E N
DESIGN OPTIMIZATION OF A WIDE BAND MEMS RESONATOR FOR EFFICIENT ENERGY
HARVESTING GOUTAM RANA, SAMIR K U M A R LAHIRI, AND CHIRASREE
ROYCHAUDHURI
L O W E R P O W E R I I
ULTRA-LOW POWER SUB-THRESHOLD SRAM CELL DESIGN TO IMPROVE READ STATIC
NOISE MARGIN 139
CHANDRABHAN KUSHWAH AND SANTOSH K. VISHVAKARMA
WORKLOAD DRIVEN POWER DOMAIN PARTITIONING 147
ARUN DOBRIYAL, RAHUL GONNABATTULA, PALLAB DASGUPTA, AND CHITTARANJAN R.
MANDAL
IMPLEMENTATION OF A NEW OFFSET GENERATOR BLOCK FOR THE LOW-VOLTAGE,
LOW-POWER SELF BIASED THRESHOLD VOLTAGE EXTRACTOR CIRCUIT 156
RITUPARNA DASGUPTA, DIPANKAR SAHA, JAGANNATH SAMANTA, SAYAN CHATTERJEE,
AND CHANDAN K U M A R SARKAR
A N A L O G V L S I D E S I G N I I
A HIGH SPEED, LOW JITTER AND FAST ACQUISITION CMOS PHASE FREQUENCY
DETECTOR FOR CHARGE P U M P PLL 166
MANAS K U M A R HATI AND TARUN KANTI BHATTACHARYYA
111
121
129
IMAGE 3
TABLE OF CONTENTS XIX
ILP BASED APPROACH FOR INPUT VECTOR CONTROLLED (IVC) TOGGLE MAXIMIZATION
IN COMBINATIONAL CIRCUITS 172
JAYNARAYAN T. TUDU, DEEPAK MALANI, AND VIRENDRA SINGH
COMPARISON OF OPAMP BASED AND COMPARATOR BASED SWITCHED CAPACITOR FILTER
180
MANODIPAN SAHOO AND BHARADWAJ AMRUTUR
T E S T A N D VERIFICATION I I
EFFECT OF MALICIOUS HARDWARE LOGIC ON CIRCUIT RELIABILITY 190
SANJAY BURMAN, A Y AN PALCHAUDHURI, RAJAT SUBHRA CHAKRABORTY, DEBDEEP
MUKHOPADHYAY, AND PRANAV SINGH
A MODIFIED SCHEME FOR SIMULTANEOUS REDUCTION OF TEST D A T A VOLUME AND
TESTING POWER 198
SRUTHI P.R. AND M. NIRMALA DEVI
REUSABLE AND SCALABLE VERIFICATION ENVIRONMENT FOR MEMORY CONTROLLERS
209
KIRAN K U M A R ABBURI, SIVA SUBRAHMANYA EVANI, SAJEEV THOMAS, AND ANUP
APREM
D E S I G N TECHNIQUES I I
DESIGN OF A FAULT-TOLERANT CONDITIONAL SUM ADDER 217
A T I N MUKHERJEE AND ANINDYA SUNDAR DHAR
SEU TOLERANT ROBUST LATCH DESIGN 223
MOHAMMED SHAYAN, VIRENDRA SINGH, ADIT D. SINGH, AND MASAHIRO FUJITA
DESIGN OF CONTENT ADDRESSABLE MEMORY ARCHITECTURE USING CARBON NANOTUBE
FIELD EFFECT TRANSISTORS 233
DEBAPRASAD DAS. AVISEK SINHA ROY, AND HAFIZUR RAHAMAN
A L G O R I T H M S A N D A P P L I C A T I O N S I I
HIGH-SPEED UNIFIED ELLIPTIC CURVE CRYPTOSYSTEM ON F P G A S USING BINARY
HUFF CURVES 243
AYANTIKA CHATTERJEE AND INDRANIL SENGUPTA
A 4 X 20 G B / S 2 9 -L PRBS GENERATOR FOR TESTING A HIGH-SPEED DAC IN
90NM CMOS TECHNOLOGY 252
MAHENDRA SAKARE, MOHIT SINGH, AND SHALABH GUPTA
IMAGE 4
X X TABLE OF CONTENTS
VLSI ARCHITECTURE FOR BIT PARALLEL SYSTOLIC MULTIPLIERS FOR SPECIAL
CLASS OF G F (2 M ) USING DUAL BASES 258
HAFIZUR RAHAMAN, JIMSON MATHEW, A.M. JABIR, AND DHIRAJ K. PRADHAN
E M E R G I N G T E C H N O L O G I E S
A SYNTHESIS METHOD FOR QUATERNARY QUANTUM LOGIC CIRCUITS 270
SUDHINDU BIKASH MANDAL, AMLAN CHAKRABARTI, AND SUSMITA SUR-KOLAY
ON THE COMPACT DESIGNS OF LOW POWER REVERSIBLE DECODERS AND SEQUENTIAL
CIRCUITS 281
LAFIFA JAMAL, MD. MASBAUL ALAM POLASH, M.A. MOTTALIB, AND HAFIZ MD.
HASAN BABU
DELAY UNCERTAINTY IN SINGLE- AND MULTI-WALL CARBON NANOTUBE
INTERCONNECTS 289
DEBAPRASAD DAS AND HAFIZUR RAHAMAN
A L G O R I T H M S A N D A P P L I C A T I O N S I I I
A FAST F P G A BASED ARCHITECTURE FOR SOBEL EDGE DETECTION 300
SANTANU HAIDER, DEBOTOSH BHATTACHARJEE, MITA NASIPURI, AND DIPAK K U M A
R BASU
SPEECH PROCESSOR DESIGN FOR COCHLEAR IMPLANTS 307
ARUN KUMARAPPAN AND P. V. RAMAKRISHNA
AN EFFICIENT TECHNIQUE FOR LONGEST PREFIX MATCHING IN NETWORK ROUTERS
317
REKHA GOVINDARAJ, INDRANIL SENGUPTA, AND SANTANU CHATTOPADHYAY
N O C A N D P H Y S I C A L D E S I G N
A FASTER HIERARCHICAL BALANCED BIPARTITIONER FOR VLSI FLOORPLANS USING
MONOTONE STAIRCASE CUTS 327
BAPI KAR, SUSMITA SUR-KOLAY, SRIDHAR H. RANGARAJAN, AND CHITTARANJAN R.
MANDAL
TEST D A T A COMPRESSION FOR NOC BASED SOCS USING BINARY ARITHMETIC
OPERATIONS 337
SANGA CHAKI AND CHANDAN GIRI
PARTICLE SWARM OPTIMIZATION BASED BIST DESIGN FOR MEMORY CORES IN MESH
BASED NETWORK-ON-CHIP 343
BIBHAS GHOSHAL, SUBHADIP KUNDU, INDRANIL SENGUPTA, AND SANTANU
CHATTOPADHYAY
IMAGE 5
TABLE OF CONTENTS XXI
P O S T E R P R E S E N T A T I O N
AN EFFICIENT MULTIPLEXER IN QUANTUM-DOT CELLULAR AUTOMATA 350
BIBHASH SEN, MANOJIT DUTTA, DIVYAM SARAN, AND BIPLAB K. SIKDAR
INTEGRATED PLACEMENT AND OPTIMIZATION FLOW FOR STRUCTURED AND REGULAR
LOGIC 352
VIKRAM SINGH SAUN, SUMAN CHATTERJEE, AND ANAND ARUNACHALAM
A NOVEL SYMBOL ESTIMATION ALGORITHM FOR LTE STANDARD 354
K KALYANI AND S. RAJARAM
IMPACT OF DUMMY POLY ON THE PROCESS-INDUCED MECHANICAL STRESS ENHANCED
CIRCUIT PERFORMANCE 357
NAUSHAD ALAM, BULUSU ANAND, AND SUDEB DASGUPTA
A NOVEL APPROACH TO VOLTAGE-DROP AWARE PLACEMENT IN LARGE SOCS IN
ADVANCED TECHNOLOGY NODES 360
BISWAJIT PATRA, SANTAN CHATTOPADHYAY, AND AMLAN CHAKRABARTI
DESIGN AND IMPLEMENTATION OF EFFICIENT VEDIC MULTIPLIER USING REVERSIBLE
LOGIC 364
P. SARAVANAN, P. CHANDRASEKAR, LIVYA CHANDRAN, NIKILLA SRIRAM, AND P.
KALPANA
DESIGN OF COMBINATIONAL AND SEQUENTIAL CIRCUITS USING NOVEL FEEDTHROUGH
LOGIC 367
SAUVAGYA RANJAN SAHOO AND KAMALA KANTA MAHAPATRA
EFFICIENT F P G A IMPLEMENTATION OF MONTGOMERY MULTIPLIER USING DSP
BLOCKS 370
ARPAN MONDAL, SANTOSH GHOSH, ABHIJIT DAS, AND DIPANWITA ROY CHOWDHURY
INDEPENDENT GATE SRAM BASED ON ASYMMETRIC GATE T O SOURCE/DRAIN
OVERLAP-UNDERLAP DEVICE F I N F E T 373
NAVEEN KAUSHIK, BRAJESH K U M A R KAUSHIK, DAVINDER KAUR, AND MANOJ K U
M A R MAJUMDER
VLSI ARCHITECTURE FOR SPATIAL DOMAIN SPREAD SPECTRUM IMAGE WATERMARKING
USING GRAY-SCALE WATERMARK 375
SUDIP GHOSH, SOMSUBHRA TALAPATRA, DEBASISH MONDAL, NAVONIL CHATTERJEE,
HAFIZUR RAHAMAN, AND SANTI P. MAITY
A PHOTONIC NETWORK ON CHIP WITH CDMA LINKS 377
SOUMYAJIT PODDAR, PRASUN GHOSAL, PRIYAJIT MUKHERJEE, SUMAN SAMUI, AND
HAFIZUR RAHAMAN
IMAGE 6
XXII TABLE OF CONTENTS
SIMULATION STUDY OF AN ULTRA THIN BODY SILICON O N INSULATOR TUNNEL
FIELD EFFECT TRANSISTOR 379
PARTHA SARATHI GUPTA, SAYAN KANUNGO, HAFIZUR RAHAMAN, AND PARTHA SARATHI
DASGUPTA
ROUTING IN NOC ON DIAMETRICAL 2D MESH ARCHITECTURE 381
PRASUN GHOSAL AND TUHIN SUBHRA DAS
I N V I T E D TALK
REVERSIBLE CIRCUITS: RECENT ACCOMPLISHMENTS AND FUTURE CHALLENGES FOR AN
EMERGING TECHNOLOGY (INVITED PAPER) 383
ROLF DRECHSLER AND ROBERT WILLE
POWER PROBLEMS IN VLSI CIRCUIT TESTING 393
FARHANA RASHID AND VISHWANI D. AGRAWAL
A U T H O R I N D E X 407 |
| any_adam_object | 1 |
| author_GND | (DE-588)1025796624 |
| building | Verbundindex |
| bvnumber | BV040408759 |
| classification_rvk | SS 4800 |
| ctrlnum | (OCoLC)812262731 (DE-599)DNB1023016354 |
| dewey-full | 621.395 621.392 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 621.392 |
| dewey-search | 621.395 621.392 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 2012 Hāora gnd-content |
| genre_facet | Konferenzschrift 2012 Hāora |
| id | DE-604.BV040408759 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:15:12Z |
| institution | BVB |
| institution_GND | (DE-588)102579673X |
| isbn | 3642314937 9783642314933 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-025261767 |
| oclc_num | 812262731 |
| open_access_boolean | |
| owner | DE-706 DE-83 DE-11 |
| owner_facet | DE-706 DE-83 DE-11 |
| physical | XXII, 408 S. graph. Darst. |
| publishDate | 2012 |
| publishDateSearch | 2012 |
| publishDateSort | 2012 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings Hafizur Rahaman ... (eds.) Berlin [u.a.] Springer 2012 XXII, 408 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 7373 Testen (DE-588)4367264-4 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2012 Hāora gnd-content VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s System-on-Chip (DE-588)4740357-3 s Field programmable gate array (DE-588)4347749-5 s Testen (DE-588)4367264-4 s Verifikation (DE-588)4135577-5 s DE-604 Rahaman, Hafizur Sonstige (DE-588)1025796624 oth VDAT 16 2012 Hāora-Shibpur Sonstige (DE-588)102579673X oth Erscheint auch als Online-Ausgabe 978-3-642-31494-0 Lecture notes in computer science 7373 (DE-604)BV000000607 7373 X:MVB text/html http://deposit.dnb.de/cgi-bin/dokserv?id=4052413&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025261767&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings Lecture notes in computer science Testen (DE-588)4367264-4 gnd Field programmable gate array (DE-588)4347749-5 gnd System-on-Chip (DE-588)4740357-3 gnd Verifikation (DE-588)4135577-5 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4367264-4 (DE-588)4347749-5 (DE-588)4740357-3 (DE-588)4135577-5 (DE-588)4312536-0 (DE-588)4117388-0 (DE-588)1071861417 |
| title | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings |
| title_auth | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings |
| title_exact_search | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings |
| title_full | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings Hafizur Rahaman ... (eds.) |
| title_fullStr | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings Hafizur Rahaman ... (eds.) |
| title_full_unstemmed | Progress in VLSI design and test 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings Hafizur Rahaman ... (eds.) |
| title_short | Progress in VLSI design and test |
| title_sort | progress in vlsi design and test 16th international symposium on vsli design and test vdat 2012 shipur india july 1 4 2012 proceedings |
| title_sub | 16th International Symposium on VSLI Design and Test, VDAT 2012, Shipur, India, July 1 - 4, 2012 ; proceedings |
| topic | Testen (DE-588)4367264-4 gnd Field programmable gate array (DE-588)4347749-5 gnd System-on-Chip (DE-588)4740357-3 gnd Verifikation (DE-588)4135577-5 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Testen Field programmable gate array System-on-Chip Verifikation Entwurfsautomation VLSI Konferenzschrift 2012 Hāora |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=4052413&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025261767&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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