Fundamentals of digital and computer design with VHDL:
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| Language: | English |
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New York, NY
McGraw Hill
2012
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| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XX, 716 S. Ill., graph. Darst. |
| ISBN: | 9780073380698 0073380695 |
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| 020 | |a 9780073380698 |c alk. paper |9 978-0-07-338069-8 | ||
| 020 | |a 0073380695 |c alk. paper |9 0-07-338069-5 | ||
| 035 | |a (OCoLC)775644527 | ||
| 035 | |a (DE-599)BVBBV039700861 | ||
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| 044 | |a xxu |c US | ||
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| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 084 | |a ZN 5405 |0 (DE-625)157455: |2 rvk | ||
| 100 | 1 | |a Sandige, Richard S. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Fundamentals of digital and computer design with VHDL |c Richard S. Sandige ; Michael L. Sandige |
| 264 | 1 | |a New York, NY |b McGraw Hill |c 2012 | |
| 300 | |a XX, 716 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Digital electronics | |
| 650 | 4 | |a Electronic digital computers |x Design and construction |x Data processing | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Sandige, Michael L. |e Sonstige |4 oth | |
| 856 | 4 | 2 | |m HBZ Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024549414&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-024549414 | ||
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| adam_text | Titel: Fundamentals of digital and computer design with VHDL
Autor: Sandige, Richard S
Jahr: 2012
Brief Contents
iiMiiiHIHIiiiUi»Hllllill|iiill!»im
Preface xiii
About the Authors xx
1 Boolean Algebra, Boolean Functions, VHDL, and Gates 1
2 Number Conversions, Codes, and Function Minimization 37
3 Introduction to Logic Circuit Analysis and Design 67
4 Combinational Logic Circuit Design with VHDL 94
5 Bistable Memory Device Design with VHDL 125
6 Simple Finite State Machine Design with VHDL 156
7 Computer Circuits 184
8 Circuit Implementation Techniques 210
9 Complex Finite State Machine Design with VHDL 227
10 Basic Computer Architectures 279
11 Assembly Language Programming for VBC1 292
12 Designing Input/Output Circuits 316
13 Designing Instruction Memory, Loading Program Counter, and Debounced Circuit 335
14 Designing Multiplexed Display Systems 357
15 Designing Instruction Decoders 379
16 Designing Arithmetic Logic Units 398
17 Completing the Design for VBC1 416
18 Assembly Language Programming for VBC1-E 425
19 Designing Input/Output Circuits for VBC1-E 458
20 Designing the Data Memory Circuit for VBC1 -E 471
21 Designing the Arithmetic, Logic, Shift, Rotate, and Unconditional Jump Circuits
forVBC1-E 482
22 Designing a Circuit to Prevent Program Execution During Manual Loading for VBC1-E 493
23 Designing Extended Instruction Memory for VBC1-E 496
24 Designing the Software Interrupt Circuits for VBC1-E 504
25 Completing the Design for VBC1-E 516
A Laboratory Experiments 528
B Obtaining Simulations via the VHDL Test Bench Program 675
C FPGA Pin Connections-Handy Reference 683
D EASY1 Tutorial 687
E Three Methods for Loading Instructions into Memory 701
Index 705
IV
Contents
WMMmmmmmmmmmm
Preface xiii
About the Authors xx
Chapter
Chapter
1
Number Conversions, Codes, and Function
Minimization 37
2.1 Introduction 37
Boolean Algebra, Boolean Functions, VHDL, and 2.2 Digital Circuits versus Analog circuits 37
Gates 1 2.2.1 Digitized Signal for the Human Heart 37
11 Introduction 1 2.2.2 Discrete Signals versus Continuous Signals 38
1.2 Basics of Boolean Algebra 1 2.3 Binary Number Conversions 38
1.2.1 Venn Diagrams 2 2 3,1 Declma1 Binary, Octal, and Hexadecimal
1.2.2 Black Boxes for Boolean Functions 3
.. _ _ . T . _ . , . 2.3.2 Conversion Techniques 40
1.2.3 Basic Logic Symbols 4 ^
1.2.4 Boolean Algebra Postulates 7 2.4 Binary Codes 45
1.2.5 Boolean Algebra Theorems 8 2-4-1 Minimum Number of Bits for Keypads and
1.2.6 Proving Boolean Algebra Theorems 9
Keyboards 45
. , , , 2.4.2 Commonly Used Codes: BCD, ASCII, and
1.3 Deriving Boolean Functions From Truth Tables 10 , .,
1.3.1 Deriving Boolean Functions Using the Is of the 2M M™]o_2 Addjtion and Conversions between
Functions 10 Binary and Reflective Gray Code 48
1.3.2 Deriving Boolean Functions Using the 0s of the 2dd 7S tTH 51
2.4.5 VHDL Design for a Letter Display System 52
Functions 11
1.3.3 Deriving Boolean Functions Using Minterms and
Maxterms 12 2-5 Karnaugh Map Reduction Method 54
1.4 Writing VHDL Designs for Simple Gate -1 Tte KamaUgh Map Expl°ref 55
Functions 15 2.5.2 Using a 2-Variable K-Map 56
1.4.1 VHDL Design for a NOT Function 15 2-53 Usin8 a 3-Variable K-Map 58
1.4.2 VHDL Design for an AND Function 17 2.5.4 Using a 4-Variable K-Map 60
1.4.3 VHDL Design for an OR Function 18 2.5.5 Don t-Care Outputs 61
1.4.4 VHDL Design for an XOR Function 19 Problems 63
1.4.5 VHDL Design for a NAND Function 21
1.4.6 VHDL Design for a NOR Function 22 Chapter 3
1.4.7 VHDL Design for an XNOR Function 24 ----------------------------------------------------------
1.4.8 vhdl Design for a buffer Function 26 Introduction to Logic Circuit Analysis and
1.4.9 VHDL Design for any Boolean Function Written DeSJQn 67
in Canonical Form 27
1.5 More about Logic Gates 30
1.5.1 Equivalent Gate Symbols 30
1.5.2 Functionally Complete Gates 31 33 Analyzing and Designing Logic Circuits 69
3.1 Introduction 67
3.2 Integrated Circuit Devices 67
1.5.3 Equivalent Gate Circuits 32 3 3-1 Analyzing and Designing Relay Logic
Circuits 69
1.5.4 Compact Description Names for Gates 32
1.5.5 International Logic Symbols for Gates 32
Problems 34
3.3.2 Analyzing IC Logic Circuits 70
3.3.3 Designing IC Logic Circuits 71
3.4 Generating Detailed Schematics 74
VI Contents
3.5 Designing Circuits in NAND/NAND and NOR/NOR 5.3.2 Characteristic Table for an S-R NAND
Form 76 Latch 132
3.6 Propagation Delay Time 78 5.3.3 Characteristic Equation for an S-R NAND
3.7 Decoders 79 Latch 133
3.7.1 Designing Logic Circuits with Decoders and 5 3-4 PS/NS Table for an S R NAND Latch 133
Single Gates 82 5.3.5 Timing Diagram for an S-R NAND Latch 133
3.8 Multiplexers 85 5-4 Designing a Simple Clock 134
3.8.1 Designing Logic Circuits with MUXs 87 5.5 Designing a D Latch 137
3.9 Hazards 88 5.5.1 Gated S-R Latch Circuit Design 137
3.9.1 Function Hazards 88 5 5-2 D Latch Circuit Design with S-R Latches 138
3.9.2 Logic Hazards 89 5.5.3 D Latch Circuit Design via the Characteristic
Table for a D Latch 139
5.5.4 Timing Diagram for a D Latch 140
4 5.5.5 Creating a Clock via a D Latch 141
5.5.6 Creating an 8-bit D Latch 142
* 5.6 Designing D Flip-Flop Circuits 143
Combinational Logic Circuit Design with VHDL 94 5 61 Designing Master-siave d FiiP-FioP
4.1 Introduction 94 Circuits 143
4.2 VHDL 94 5 6-2 Designing D Flip-Flop Circuits with S-R NAND
Problems 91
4.3 The Library Part 95 Latches 146
4.4 The Entity Declaration 96 563 TiminS Dia8ram for Positlve Edge-Triggered D
J Flip-Flop 149
4.5 The Architecture Declaration 97 ,. .. ™
. ^ ^ , ,^ ^. , Problems 150
4.5.1 Comments about a Dataflow Design Style 98
4.5.2 Comments about a Behavioral Design Style 98
4.5.3 Comments about a Structural Design Style 98 Chapter O
4.6 Dataflow Design Style 99 --------------------------------------------------------------------------•
4.7 Behavioral Design style 102 Simple Finite State Machine Design with VHDL 156
4.8 Structural Design Style 106 6.1 Introduction 156
4.9 Implementing with Wires and Buses 112 6.2 Synchronous Circuits 156
4.10 VHDL Examples 116 6.3 Creating D-type Flip-Flops in VHDL 157
4.10.1 Design with Scalar Inputs and Outputs 117 6.4 Designing Simple Synchronous Circuits 158
4.10.2 Design with Vector Inputs and Outputs 118 6.5 Counter Design Using the Algorithmic Equation
4.10.3 Common VHDL Constructs 120 Method 159
Problems 121 6.6 Nonconventional Counter Design Using the
Algorithmic Equation Method 167
Chaotpr 5 ^ Counter Design Using the Arithmetic Method 170
6.8 Frequency Division (Slowing Down a Fast Clock
Bistable Memory Device Design with VHDL 125 Frequency) m
6.9 Counter Design Using the PS/NS Tabular
5.1 Introduction 125 Method m
5.2 Analyzing an S-R NOR Latch 125 6 10 Nonconventional Counter Design Using the ps/ns
5.2.1 Simple On/Off Light Switch 125 Tabular Method 177
5.2.2 Circuit Delay Model for an S-R NOR Latch 127 Problems 178
5.2.3 Characteristic Table for an S-R NOR Latch 128
5.2.4 Characteristic Equation for an S-R NOR _
Latch 129 Chapter 7
5.2.5 PS/NS Table for an S-R NOR Latch 129 ------------------------------------------------------------------------
5.2.5 Timing Diagram for an S-R NOR Latch 130 Computer Circuits 184
5.3 Analyzing an S-R NAND Latch 132 7.1 Introduction 184
5.3.1 Circuit Delay Model for an S-R NAND 7.2 Three-State Outputs and the Disconnected
Latch 132 State 184
Contents VII
7.3 Data Bus Sharing for a Microcomputer System 187 9.5 Designing Compact Encoded State Machines with
7.4 More about XOR and XNOR Symbols and Moore Outputs 235
Functions 190 9.6 Designing One-Hot Encoded State Machines with
7.4.1 Odd and Even Functions 191 Moore Outputs 237
7.4.2 Single-Bit Error Detection System 192 9.7 Designing Compact Encoded State Machines with
7.4.3 Comparators and Greater Than Circuits 194 Moore and Mealy Outputs 241
7.5 Adder Design 197 9.8 Designing One-Hot Encoded State Machines with
7.5.1 Designing a Half Adder Module 197 Moore and Mealy Outputs 243
7.5.2 Designing a Full Adder Module 198 9.9 Using the Algorithmic Equation Method to Design
7.6 Designing and Using Ripple-Carry Adders and Complex State Machines 245
Subtracters 200 9.10 Improving the Reliability of Complex State Machine
7.7 Propagation Delay Time for Ripple-Carry Designs 251
Adders 203 9.11 Additional State Machine Design Methods 255
7.8 Designing Carry Look-Ahead Adders 203 9.11.1 Two-Assignment PS/NS Method 256
7.9 Propagation Delay Time for Carry Look-Ahead 9-11-2 Hybrid PS/NS Method 259
Adders 206 Problems 262
Problems 206
8
Chapter
10
Chapter _
-------------------------------------------------------------------------• Basic Computer Architectures 279
Circuit Implementation Techniques 210 10.1 introduction 279
8.1 Introduction 210 10-2 Generic Data-Processing System or Computer 279
8.2 Programmable Logic Devices 210 10.3 Harvard-Type Computer and RISC
8.2.1 PROMsandLUTs 212 Architecture 280
8.2.2 PLAs 213 10.4 Princeton (von Neumann)-Type Computer and CISC
8.2.3 PALsorGALs 213 Architecture 282
8.2.4 Designing with PROMs or LUTs 214 10.5 Overview of VBC1 (Very Basic Computer 1) 283
8.2.5 Designing with PLAs 215 10.6 Design Philosophy of VBC1 283
8.2.6 Designing with PALs or GALs 216 10.7 Programmer s Register Model for VBC1 286
8.3 Positive Logic Convention and Direct Polarity 10.8 Instruction Set Architecture for VBC1 287
Indication 217 10.g Format for Writing Assembly Language
8.3.1 Signal Names 217 Programs 289
8.3.2 Analyzing Equivalent Circuits for the PLC and Problems 290
the DPI Systems 218
8.4 More about MUXs and DMUXs 221 uu
8.4.1 Designing MUX Trees 223 Chapter______________________________________
8.4.2 Designing DMUX Trees 223
Problems 224 Assembly Language Programming for VBC1 292
11.1 Introduction 292
Chapter
11.2 Instruction Set for VBC1 292
11.3 The IN Instruction 293
Complex Finite State Machine Design with 11.4 The out instruction 296
VHDL 227 11-5 The MOV Instruction 298
11.6 The LOADI Instruction 300
11.7 The ADDI Instruction 301
11.8 The ADD Instruction 303
9.1 Introduction 227
9.2 Designing with the Two-Process PS/NS Method 228
9.3 Explanation of CPLDs and FPGAs and State
Machine Encoding Styles 231 11.9 The SR0 Instruction 304
9.4 Summary of Finite State Machine Models 234 111° The JNZ Instruction 306
VIII Contents
11.11 Programming Examples and Techniques for 4 A
vrpi ™» Chapter It
VBC1 308
11.11.1 Unconditional Jump 308 ¦» . - ...... ¦.». » .-_
11112 Labels 308 Designing Multiplexed Display Systems 357
11.11.3 Loop Counter 309 14.1 Introduction 357
11.11.4 Program Runs Amuck 310 14.2 Multiplexed Display System for Four 7-Segment LED
11.11.5 Subtraction Instruction 310 Displays 357
11.11.6 Multiply Instruction 312 14.3 Designing a Multiplexed Display System Using
11.11.7 Divide Instruction 312 VHDL 360
Problems 312 14.3.1 Designing Module 1: A 4-to-l MUX Array 360
14.3.2 Designing Module 2: A HEX Display
.in Decoder 361
Chapter £. 14.3.3 Designing Module 3: A 2-bit Counter and a
* Frequency Divider 362
Designing Input/Output Circuits 316 14.3.4 Designing Module 4: A 2-to-4 Decoder 364
12.1 Introduction 316 14.4 Complete Design of a Multiplexed Display System
12.2 Designing Steering Circuits 316 Using a Flat Design Approach 364
12.3 Designing Bus Steering Circuits 318 14-5 Complete Design of a Multiplexed Display System
12.4 Designing Loadable Register Circuits 319 Using a Hierarchal Design Approach 367
12.5 Designing Input Circuits 321 146 Dining a Word Display System Using a Flat
12.5.1 Designing an Input Circuit Driven by Four Slide
Switches 323 Problems 377
12.6 Designing Output Circuits 324
12.6.1 Designing an Output Circuit to Drive Four Chapter 13
LEDs 325 -------------------------------------------------------------------------•
12.6.2 Designing an Output Circuit to Drive a Designing Instruction Decoders 379
7-Segment Display 326
., ,™ , , .., . .^_ , 15.1 Introduction 379
12.6.3 A Closer Look at the Circuitry for
Display 0 328 ^ .2 Purpose of the Instruction Decoder 379
12.7 Combining Input and Output Circuits to Form a 15-3 Instruction Decoder Truth Tables for the IN, OUT,
Simple I/O System 329 and MOV Instructions 380
12.8 Alternate VHDL Design Styles 332 15.4 Designing an Instruction Decoder for the IN
o ki _ iii Instruction 382
Problems 333
15.5 Designing an Instruction Decoder for the OUT and
.. - MOV Instructions 383
Chapter lO 15.6 Instruction Decoder Truth Table for the LOADI
~ • Instruction 384
Designing Instruction Memory, Loading Program 15.7 instruction Decoder Truth Table for the addi
Counter, and Debounced Circuit 335 instruction 385
13.1 Introduction 335 15.8 Instruction Decoder Truth Table for the ADD
13.2 Designing an Instruction Memory 335 Instruction 386
13.2.1 Coding Alterations for Instruction Memory 337 15-9 Instruction Decoder Truth Table for the SR0
13.2.2 Initializing Instruction Memory for VBC1 at Instruction 387
Startup 339 15.10 Designing an Instruction Decoder for the SR0
13.3 Designing a Loading Program Counter 342 Instruction 388
13.4 Designing a Debounced One-Pulse Circuit 345 15-11 Instruction Decoder Truth Table for the JNZ
13.5 Design Verification for a Debounced One-Pulse
Circuit 348 15.12 Designing an Instruction Decoder for the JNZ
Problems 355
Instruction 391
15.13 Designing an Instruction Decoder for VBC1 393
Problems 393
Contents IX
Chapter 16 Chapter 19
Designing Arithmetic Logic Units 398 Designing Input/Output Circuits for VBC1-E 458
16.1 Introduction 398 19.1 Introduction 458
16.2 Utilization of the Arithmetic Logic Unit 398 19.2 Designing the Input Circuit for VBC1-E 458
16.3 Designing the LOADI Instruction Part of the 19.3 Instruction Decoder Truth Table for the Modified IN
ALU 399 Instruction for VBC1-E 460
16.4 Designing the ADDI Instruction Part of the 19.4 Designing the Output Circuit for VBC1-E 462
ALU 400 19.5 Instruction Decoder Truth Table for the Modified
16.5 Designing the ADD Instruction Part of the ALU 401 OUT Instruction for VBC1-E 464
16.6 Designing the SRO Instruction Part of the ALU 401 19.6 Designing an Instruction Decoder for the Modified
16.7 Designing an ALU for VBC1 402 IN and OUT Instructions for VBC1-E 466
16.8 Additional Circuit Designs with VHDL 403 i9-7 Designing an Instruction Decoder for the LOADI,
16.8.1 Designing Additional ALU Circuits 403 ADDI, and JNZ Instructions for VBC1-E 467
16.8.2 Designing Shifter Circuits 406 Problems 468
16.8.3 Designing Barrel Shifter Circuits 409
16.8.4 Designing Shift Register Circuits 412 Chapter 20
Problems 414 -------------------------------------------------------------------------•
Designing the Data Memory Circuit for VBC1 -E 471
Chapter 17 20.1 Introduction 471
-------------------------------------------------------------------------• 20.2 Designing the Data Memory for VBC1-E 471
Completing the Design for VBC1 416 20.3 Designing Circuits to Select the Registers and Data
17.1 Introduction 416 forVBCl-E 475
17.2 Designing a Running Program Counter 416 20.4 Instruction Decoder Truth Tables for the STORE and
17.3 Combining a Loading and a Running Program FETCH Instructions for VBC1-E 475
Counter 419 20.5 Designing an Instruction Decoder for the STORE
17.4 Designing a Run Frequency Circuit and a Speed and FETCH Instructions for VBC1-E 478
Circuit 421 20.6 Designing an Instruction Decoder for the MOV
17.5 Designing Circuits to Provide a Loader for Instruction for VBC1-E 479
Instruction Memory for VBC1 423 Problems 480
Problems 424
Chapter
18
Chapter
21
Designing the Arithmetic, Logic, Shift, Rotate, and
Assembly Language Programming for VBC1-E 425 Unconditional Jump Circuits for VBC1-E 482
18.1 Introduction 425 21-1 Introduction 482
18.2 Instruction Summary 425 21,2 Designing the Arithmetic and Logic Instructions Part
,__ ¥ int t .. , _ _ t. .,_ oftheALUforVBCl-E 482
18.3 Input, Output, and Interrupt Instructions 427
, . , ., _ . .. ... 21.3 Designing the Instruction Decoder for the Arithmetic
18.4 Data Memory Instructions 432 ..1,,J, fc_^fc.™nr *°*
18.5 Arithmetic and Logic Instructions 434
and Logic Instructions for VBC1-E 484
21.4 Designing the Shift and Rotate Instructions Part of
18.6 Shift and Rotate Instructions 437 the ALU for VBC1-E 485
18.7 Jump, Jump Relative, and Halt Instructions 439 21 5 Designing the Instruction Decoder for the Shift and
18.8 More about Interrupts and Assembler Rotate Instructions for VBC1-E 486
Directives 443
21.6 Designing the JMP and JMPR Circuits for
18.9 Complete Instruction Set Summary for VBC1-E 488
VBC1-E 448 21.7 Designing the Instruction Decoder for the JMP and
Problems 449 JMPR Instructions for VBC IE 489
Problems 490
Contents
Chapter 22 Chapter 25
Designing a Circuit to Prevent Program Execution Completing the Design for VBC1-E 516
During Manual Loading for VBC1-E 493 25.1 introduction 516
22.1 Introduction 493 25.2 Designing a Debounced One-Pulse Trigger Interrupt
22.2 Designing a Circuit to Modify Manual Loading for Circuit and Modifying the RPC Circuit for
VBC1-E 493 VBC1-E 516
22.3 Modifying the Instruction Decoder for Manual 25.3 Designing Circuits for Displaying the Signal RETA
Loading for VBC1-E 495 forVBCl-E 521
Problems 495 25.4 Designing Circuits to Provide a Loader for
Chapter
23
Instruction Memory for VBC1-E 525
Problems 525
Appendices
Designing Extended Instruction Memory for
VBC1-E 496 A Laboratory Experiments 528
23.1 Introduction 496 Experiment 1A: Designing and Simulating Gates 528
23.2 Modifying the Instruction Memory to Add Extended Experiment 1B: Completing the Design Cycle 534
Instruction Memory for VBC1-E 496 Experiment 2: Designing and Testing a Keypad Encoder
23.3 Modifying the Running Program Counter Circuit for System 539
VBC1-E 500 Experiments: Designing and Testing a Check Gates
23.4 Modifying the Proper Address Circuit for System 542
VBC1-E 501 Experiment 4: Designing and Testing a Custom Decimal
23.5 Modifying the Loading Program Counter Circuit for Display Decoder System 546
VBC1-E 501 Experiment 5A: Designing and Testing a D Latch and a
23.6 Modifying the JMPR Circuit for VBC1-E 502 D Flip-Flop with a CLR Input 549
Problems 502 Experiment 5B: Designing and Testing an 8-bit Register
and a D Flip-Flop with a PRE Input 553
04 Experiment 6A: Designing and Testing a Simple Counter
Chapter £.t__________________________________ System-A One-Hot Up Counter with 8
* Bits 558
Designing the Software Interrupt Circuits for Experiment 6B: Designing and Testing a Simple Counter
VBC1 -E 504 System-A Gray Code Counter with
24.1 Introduction 504 2 Bits 562
24.2 Designing the Modified Circuit for the Running Experiment 6C: Designing and Testing a Simple
Program Counter and the Select Circuit for Nonconventional Counter System-A
VBC1-E 504 Robot Eye Circuit 565
24.3 Designing the Circuit to Store PCPLUS1 for Experiment 60: Designing and Testing a Simple
VBC1-E 509 Nonconventional Counter-A Smiley Face
24.4 Instruction Decoder Truth Tables for the INT and Circuit 569
IRET Instructions for VBC1-E 510 Experiment 7A: Designing and Testing a Simple Error
24.5 Designing the Instruction Decoder for the INT and Detection System Using a Flat Design
IRET Instructions for VBC1-E 511 Approach 572
Problems 513 Experiment 7B: Designing and Testing a 4-bit Simple
Adder-Subtractor System Using a
Hierarchal Design Approach 577
Contents XI
Experiment 8: Designing and Testing a LUT B Obtaining Simulations via the VHDL Test
Design System Using a Flat Design Bench Program 675
Approach 580
Experiment 9A: Designing and Testing a One-Hot Up/ B.1 Introduction 675
Down Counter System Using a Flat Design B-2 Example 1-Combinational Logic Design (project:
Approach 584 AND_3) 675
Experiment 9B: Designing and Testing a 10-State Counter B-3 Example 2-Synchronous Sequential Logic Design
System Using a Hierarchal Design (project: DFF) 679
Approach 589
Experiment 10: Working with EASY1 (Editor/Assembler/ C FPGA Pin Connections-Handy
Simulator) for VBC1 593 Reference 683
Experiment 11: Writing and Simulating Programs for C.1 BASYS2Board 683
VBClwithEASYl 598 c 2 NEXYS2Board 684
Experiment 12: Designing and Testing VBC1 (Data Path c.3 Memory Loader vo pjn Connections for the FPGAs
Unit) 600 on the BASYS 2 and NEXYS 2 Board 685
Experiment 13: Designing and Testing VBC1 (Instruction C-4 FX2 M1B (Module Interface Board)-Add-on Board
Memory Unit) 605 for NEXYS 2 686
Experiment 14: Designing and Testing VBC1 (Monitor
System) 609 Q EASY-| Tutorial 687
Experiment 15: Designing and Testing VBC1 (Instruction
Decoder) 613
Experiment 16: Designing and Testing VBC1 (Arithmetic
Logic Unit) 617 D-3 EASY 1 Layout 687
Experiment 17: Designing and Testing VBC1 (Final D-4 How to Use EASY1 689
Hardware Design for VBC1) 621 D.5 Example 1-A Simple Input/Output Program 689
Experiment 17L: Designing a Loader for Instruction D.6 Example 2-Input/Output Program Modified to Run
Memory for VBC1 626 Continuously 695
Experiment 18 Writing Assembly Language Programs 0.7 Example 3-A Simple State Machine Program 696
and Running Them on VBC1 632 0.8 Example 4-A Complex State Machine
Experiment 19: Designing and Testing VBC1-E (IN, OUT, Program 696
and Unchanged Instructions) 635 D.9 Example 5-Generating Time Delays 698
Experiment 20: Designing and Testing VBC1-E (MOV and D.10 Using EASY1 to Generate Machine Code for
Data Memory Instructions) 640 VBC1 699
Experiment 21: Designing and Testing VBC1-E (Almost
All Instructions) 645 E Three Methods for Loading Instructions
Experiment 22: Designing and Testing VBC1-E (Modified into Memory 701
Manual Loading) 651 _., T .. .. ., _-,
^ E.1 Loading Memory Manually 701
Experiment 23: Designing and Testing VBC1-E (Add
Extended Instruction Memory) 654
Experiment 24: Designing and Testing VBC1-E (INT and
IRET Instructions) 658
Experiment 25: Designing and Testing VBC1-E (Final Index 705
Hardware Design for VBC1-E) 663
Experiment 25L: Designing a Loader for Instruction
Memory for VBC1-E 668
D.1 Introduction 687
0.2 EASY1 Screen or GUI 687
E.2 Initializing Memory at Startup 702
E.3 Loading Memory via the Memory Loader
Program 703
|
| any_adam_object | 1 |
| author | Sandige, Richard S. |
| author_facet | Sandige, Richard S. |
| author_role | aut |
| author_sort | Sandige, Richard S. |
| author_variant | r s s rs rss |
| building | Verbundindex |
| bvnumber | BV039700861 |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.D5 |
| callnumber-search | TK7868.D5 |
| callnumber-sort | TK 47868 D5 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4904 ZN 5405 |
| ctrlnum | (OCoLC)775644527 (DE-599)BVBBV039700861 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV039700861 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T00:09:18Z |
| institution | BVB |
| isbn | 9780073380698 0073380695 |
| language | English |
| lccn | 2011033683 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-024549414 |
| oclc_num | 775644527 |
| open_access_boolean | |
| owner | DE-634 DE-83 DE-859 |
| owner_facet | DE-634 DE-83 DE-859 |
| physical | XX, 716 S. Ill., graph. Darst. |
| publishDate | 2012 |
| publishDateSearch | 2012 |
| publishDateSort | 2012 |
| publisher | McGraw Hill |
| record_format | marc |
| spelling | Sandige, Richard S. Verfasser aut Fundamentals of digital and computer design with VHDL Richard S. Sandige ; Michael L. Sandige New York, NY McGraw Hill 2012 XX, 716 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Datenverarbeitung Digital electronics Electronic digital computers Design and construction Data processing VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd rswk-swf VHDL (DE-588)4254792-1 s DE-604 Sandige, Michael L. Sonstige oth HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024549414&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Sandige, Richard S. Fundamentals of digital and computer design with VHDL Datenverarbeitung Digital electronics Electronic digital computers Design and construction Data processing VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4254792-1 |
| title | Fundamentals of digital and computer design with VHDL |
| title_auth | Fundamentals of digital and computer design with VHDL |
| title_exact_search | Fundamentals of digital and computer design with VHDL |
| title_full | Fundamentals of digital and computer design with VHDL Richard S. Sandige ; Michael L. Sandige |
| title_fullStr | Fundamentals of digital and computer design with VHDL Richard S. Sandige ; Michael L. Sandige |
| title_full_unstemmed | Fundamentals of digital and computer design with VHDL Richard S. Sandige ; Michael L. Sandige |
| title_short | Fundamentals of digital and computer design with VHDL |
| title_sort | fundamentals of digital and computer design with vhdl |
| topic | Datenverarbeitung Digital electronics Electronic digital computers Design and construction Data processing VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd |
| topic_facet | Datenverarbeitung Digital electronics Electronic digital computers Design and construction Data processing VHDL (Computer hardware description language) VHDL |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024549414&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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