Transactional memory:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
[San Rafael, Calif.]
Morgan & Claypool
2010
|
| Ausgabe: | 2. ed. |
| Schriftenreihe: | Synthesis lectures on computer architecture
11 |
| Schlagworte: | |
| Beschreibung: | XIV, 247 S. graph. Darst. |
| ISBN: | 9781608452354 |
Internformat
MARC
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| 035 | |a (OCoLC)756293250 | ||
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| 084 | |a ST 175 |0 (DE-625)143603: |2 rvk | ||
| 100 | 1 | |a Harris, Tim |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Transactional memory |c Tim Harris ; James Larus ; Ravi Rajwar |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a [San Rafael, Calif.] |b Morgan & Claypool |c 2010 | |
| 300 | |a XIV, 247 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Synthesis lectures on computer architecture |v 11 | |
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| 689 | 0 | 1 | |a Robustheit |0 (DE-588)4126481-2 |D s |
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| 700 | 1 | |a Larus, James |e Verfasser |4 aut | |
| 700 | 1 | |a Rajwar, Ravi |e Verfasser |4 aut | |
| 830 | 0 | |a Synthesis lectures on computer architecture |v 11 |w (DE-604)BV023068349 |9 11 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-024421436 | ||
Datensatz im Suchindex
| _version_ | 1804148396496257024 |
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| any_adam_object | |
| author | Harris, Tim Larus, James Rajwar, Ravi |
| author_facet | Harris, Tim Larus, James Rajwar, Ravi |
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| author_sort | Harris, Tim |
| author_variant | t h th j l jl r r rr |
| building | Verbundindex |
| bvnumber | BV039569896 |
| classification_rvk | ST 175 |
| ctrlnum | (OCoLC)756293250 (DE-599)BSZ34367677X |
| discipline | Informatik |
| edition | 2. ed. |
| format | Book |
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| id | DE-604.BV039569896 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T00:06:28Z |
| institution | BVB |
| isbn | 9781608452354 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-024421436 |
| oclc_num | 756293250 |
| open_access_boolean | |
| owner | DE-Aug4 DE-384 |
| owner_facet | DE-Aug4 DE-384 |
| physical | XIV, 247 S. graph. Darst. |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Morgan & Claypool |
| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spelling | Harris, Tim Verfasser aut Transactional memory Tim Harris ; James Larus ; Ravi Rajwar 2. ed. [San Rafael, Calif.] Morgan & Claypool 2010 XIV, 247 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Synthesis lectures on computer architecture 11 Transaktionssystem (DE-588)4195506-7 gnd rswk-swf Robustheit (DE-588)4126481-2 gnd rswk-swf Gemeinsamer Speicher (DE-588)4294156-8 gnd rswk-swf Gemeinsamer Speicher (DE-588)4294156-8 s Robustheit (DE-588)4126481-2 s Transaktionssystem (DE-588)4195506-7 s DE-604 Larus, James Verfasser aut Rajwar, Ravi Verfasser aut Synthesis lectures on computer architecture 11 (DE-604)BV023068349 11 |
| spellingShingle | Harris, Tim Larus, James Rajwar, Ravi Transactional memory Synthesis lectures on computer architecture Transaktionssystem (DE-588)4195506-7 gnd Robustheit (DE-588)4126481-2 gnd Gemeinsamer Speicher (DE-588)4294156-8 gnd |
| subject_GND | (DE-588)4195506-7 (DE-588)4126481-2 (DE-588)4294156-8 |
| title | Transactional memory |
| title_auth | Transactional memory |
| title_exact_search | Transactional memory |
| title_full | Transactional memory Tim Harris ; James Larus ; Ravi Rajwar |
| title_fullStr | Transactional memory Tim Harris ; James Larus ; Ravi Rajwar |
| title_full_unstemmed | Transactional memory Tim Harris ; James Larus ; Ravi Rajwar |
| title_short | Transactional memory |
| title_sort | transactional memory |
| topic | Transaktionssystem (DE-588)4195506-7 gnd Robustheit (DE-588)4126481-2 gnd Gemeinsamer Speicher (DE-588)4294156-8 gnd |
| topic_facet | Transaktionssystem Robustheit Gemeinsamer Speicher |
| volume_link | (DE-604)BV023068349 |
| work_keys_str_mv | AT harristim transactionalmemory AT larusjames transactionalmemory AT rajwarravi transactionalmemory |