APA (7th ed.) Citation

Müller, R. (1993). Bounds for linear VLSI layout problems: = Schranken für lineare VLSI-Layout-Probleme.

Chicago Style (17th ed.) Citation

Müller, Rudolf. Bounds for Linear VLSI Layout Problems: = Schranken Für Lineare VLSI-Layout-Probleme. 1993.

MLA (9th ed.) Citation

Müller, Rudolf. Bounds for Linear VLSI Layout Problems: = Schranken Für Lineare VLSI-Layout-Probleme. 1993.

Warning: These citations may not always be 100% accurate.