Structured analog CMOS design:
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Berlin [u.a.]
Springer
2008
|
| Series: | Analog circuits and signal processing
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | 350 S. Ill., graph. Darst. |
| ISBN: | 9781402085727 1402085729 |
Staff View
MARC
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| 100 | 1 | |a Stefanović, Danica |e Verfasser |0 (DE-588)139721592 |4 aut | |
| 245 | 1 | 0 | |a Structured analog CMOS design |c Danica Stefanovic ; Maher Kayal |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2008 | |
| 300 | |a 350 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 490 | 0 | |a Analog circuits and signal processing | |
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Record in the Search Index
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|---|---|
| adam_text | STRUCTURED ANALOG CMOS DESIGN DANICA STEFANOVIC AND MAEHER KAYAL ECOLE
POLYTECHNIQUE FEDERALE DE LAUSANNE, SWITZERLAND SPRINGER TABLE OF
CONTENTS 1 INTRODUCTION 1.1 THE OBJECTIVES OF THIS WORK 2 1.2 STRUCTURED
ANALOG DESIGN 3 1.3 TRANSISTOR-LEVEL DESIGN BASED ON THE DEVICE
INVERSION LEVEL 4 1.4 CAD TOOLS FOR ANALOG DESIGN ASSISTANCE 5 1.5
PRACTICAL DESIGN EXAMPLE 5 1.6 BOOK ORGANIZATION 5 2 TRANSISTOR LEVEL
DESIGN 2.1 MOS TRANSISTOR MODEL 7 2.1.1 OVERVIEW OF MOS MODELS 8 2.1.2
MOS MODEL ORIENTED TOWARDS TRANSISTOR-LEVEL DESIGN 10 2.2 TRANSISTOR
DESIGN PARAMETERS 10 2.2.1 TRANSISTOR SYMMETRY AND VOLTAGE DEFINITIONS
11 2.2.2 OPERATING REGIONS 12 2.2.3 STRONG INVERSION, PINCH-OFF VOLTAGE
AND SLOPE FACTOR 13 2.2.4 WEAK INVERSION 15 2.2.5 DRAIN CURRENT AND
SPECIFIC CURRENT 16 2.2.6 SATURATION DRAIN CURRENT AND SATURATION
VOLTAGE 18 2.2.7 INVERSION FACTOR AS A MEASURE OF THE DEVICE INVERSION
LEVEL 20 2.2.8 TRANSCONDUCTANCES 20 2.2.9 NORMALIZED TRANSCONDUCTANCE 22
2.2.10 CAPACITANCES 24 2.2.11 INTRINSIC GAIN 26 2.2.12 TRANSITION
FREQUENCY 27 2.2.13 INTRINSIC NOISE 27 2.3 DESIGN APPROACH 28 2.3.1
DESIGN PARAMETERS AND DESIGN VARIABLES 28 2.3.2 TABLE OF DESIGN
PARAMETERS AS FUNCTIONS OF THE DESIGN VARIABLES 30 2.3.3 ANALYSES OF
DESIGN PARAMETERS AS FUNCTIONS OF THE DESIGN VARIABLES 32 2.3.4 DESIGN
STEPS 40 2.3.5 DESIGN RECIPES 41 2.4 CONCLUSION 46 BIBLIOGRAPHY 48 3
BSIM TO EKV CONVERSION 3.1 MOTIVATION AND PURPOSE 51 3.2 CONVERSION
CONCEPT 52 3.3 BSIM VERSUS EKV, THE FUNDAMENTAL DIFFERENCES AND THE
CONVERSION ALGORITHM GUIDELINES 53 3.4 CONVERSION ALGORITHM 55 3.4.1
INITIALIZATION 57 3.4.2 SPECIFIC CURRENT CALCULATION 59 3.4.3 EXTRACTION
OF PARAMETERS VTO, GAMMA AND PHI 60 3.4.4 EXTRACTION OF PARAMETERS LETA,
WETA, AND LK, QO 60 3.4.5 EXTRACTION OF PARAMETERS KP, E0 61 3.4.6
EXTRACTION OF PARAMETERS RSH, DL 62 3.4.7 EXTRACTION OF PARAMETERS
UCRIT, LAMBDA 62 3.4.8 EXTRACTION OF PARAMETERS IBA, IBB, IBN 64 3.4.9
EXTRACTION OF PARAMETERS TCV, BEX, AND UCEX 64 3.4.10 EXTRACTION OF
PARAMETERS KF, AF 64 3.5 CONVERSION RESULTS 64 3.5.1 THE 0.18 |XM CMOS
TECHNOLOGY CONVERSION EXAMPLE 68 3.5.2 RESULTS INTERPRETATION FOR ANALOG
DESIGN 72 VIII 3.6 CONCLUSION 73 3.7 DOWNLOAD 73 BIBLIOGRAPHY 74 4 BASIC
ANALOG STRUCTURES 4.1 INTRODUCTION 77 4.2 BASIC ANALOG STRUCTURES
LIBRARY 77 4.2.1 TRANSISTOR IN A DESIGN ENVIRONMENT 80 4.3 STRUCTURED
DESIGN APPROACH 81 4.3.1 CIRCUIT PARTITIONING 82 4.3.2 DERIVATION OF THE
SPECIFICATIONS 83 4.4 TRANSCONDUCTANCE STRUCTURES 87 4.4.1 COMMON SOURCE
87 4.4.2 COMMON DRAIN 89 4.4.3 COMMON GATE 92 4.4.4 CASCODE AND FOLDED
CASCODE 95 4.4.5 DIFFERENTIAL PAIR 98 4.5 LOAD STRUCTURES 107 4.5.1
SIMPLE CURRENT MIRROR 107 4.5.2 CASCODE CURRENT MIRROR 109 4.6 BIAS
STRUCTURES 110 4.6.1 VOLTAGE BIAS 110 4.6.2 CURRENT BIAS 112 4.7
CONCLUSION 114 BIBLIOGRAPHY 115 5 PROCEDURAL DESIGN SCENARIOS 5.1
INTRODUCTION 117 5.1.1 PROCEDURAL DESIGN SEQUENCE FOR AN ANALOG
AMPLIFIER 117 5.1.2 DEFINITIONS OF THE CIRCUIT-LEVEL DESIGN PARAMETERS
120 5.2 PROCEDURAL DESIGN SCENARIO FOR A FOLDED-CASCODE OTA 127 5.2.1
CIRCUIT-LEVEL DESIGN PARAMETERS 127 5.2.2 FREQUENCY ANALYSIS 130 5.2.3
CIRCUIT PARTITIONING 134 5.2.4 DERIVATION OF THE SPECIFICATIONS 134
5.2.5 PROCEDURAL DESIGN SEQUENCE 136 5.3 PROCEDURAL DESIGN SCENARIO FOR
A FULLY-DIFFERENTIAL FOLDED CASCODEOTA 141 5.3.1 CIRCUIT-LEVEL DESIGN
PARAMETERS 143 5.3.2 FREQUENCY ANALYSIS 144 5.3.3 CIRCUIT PARTITIONING
147 5.3.4 DERIVATION OF THE SPECIFICATIONS 149 5.3.5 PROCEDURAL DESIGN
SEQUENCE 152 5.4 PROCEDURAL DESIGN SCENARIO FOR A MILLER OPERATIONAL
AMPLIFIER 156 5.4.1 CIRCUIT-LEVEL DESIGN PARAMETERS 157 5.4.2 FREQUENCY
ANALYSIS 158 5.4.3 CIRCUIT PARTITIONING 160 5.4.4 DERIVATION OF THE
SPECIFICATIONS 162 5.4.5 PROCEDURAL DESIGN SEQUENCE 163 5.5 CONCLUSION
166 BIBLIOGRAPHY 167 6 PAD TOOL 6.1 INTRODUCTION 169 6.1.1 OVERVIEW OF
ANALOG CAD TOOLS 170 6.1.2 PROCEDURAL ANALOG DESIGN (PAD) TOOL 171 6.2
PAD STRUCTURE 173 6.2.1 CHART-BASED GRAPHICAL INTERFACE 174 6.3 BASIC
ANALOG STRUCTURES LIBRARY 174 6.4 PROCEDURAL DESIGN SCENARIOS 177 6.4.1
EXAMPLE OF THE PROCEDURAL DESIGN FOR A FOLDED CASCODE OTA 178 6.4.2
EXAMPLE OF THE PROCEDURAL DESIGN FOR A MILLER OPERATIONAL AMPLIFIER 178
6.5 BSIM AND EKV MODEL LIBRARY FILE INPUT 183 6.6 CONCLUSION 184 6.7
DOWNLOAD 184 BIBLIOGRAPHY 185 7 TOPOLOGY VARIANTS 7.1 BASIC CONCEPT 189
7.1.1 DESIGN EXAMPLE: FULLY-DIFFERENTIAL FOLDED CASCODE OTA AND ITS CMFB
AMPLIFIER 189 7.2 GAIN ENHANCEMENT - TWO STAGES 192 7.2.1 MILLER
COMPENSATION 193 7.2.2 CASCODE MILLER COMPENSATION 196 7.3 GAIN
ENHANCEMENT - GAIN BOOSTING 200 7.4 INPUT COMMON-MODE RANGE ENHANCEMENT
- COMPLEMENTARY DIFFERENTIAL PAIR 206 7.5 DIFFERENTIAL INPUT RANGE
ENHANCEMENT - LINEARIZED DIFFERENTIAL PAIR 210 7.6 REJECTION OF THE
DIFFERENTIAL SIGNAL IN A COMMON-MODE SIGNAL - CASCODED CURRENT BIAS
SOURCES 214 7.7 CMFB STABILITY IMPROVEMENT- SPLIT BIAS SOURCES 216 7.8
CONCLUSION 219 BIBLIOGRAPHY 220 XI 8 PRACTICAL EXAMPLE: THE DESIGN OF
ANALOG AMPLIFIERS IN THE DELTA-SIGMA MODULATOR SYSTEM 8.1 DELTA-SIGMA
MODULATOR SYSTEM 221 8.1.1 DESIGN FLOW 223 8.1.2 VERIFICATION OF THE
PERFORMANCE 225 8.2 DERIVATION OF THE TESTBENCH 227 8.2.1
FULLY-DIFFERENTIAL DIFFERENCE AMPLIFIER 227 8.2.2 FULLY-DIFFERENTIAL
AMPLIFIER IN THE FIRST INTEGRATOR 229 8.2.3 FULLY-DIFFERENTIAL AMPLIFIER
IN THE SECOND INTEGRATOR 230 8.3 TOPOLOGY SELECTION 233 8.3.1 ANALYSIS
OF TECHNOLOGY LIMITS 234 8.3.2 TOPOLOGY VARIANTS TO FULFILL THE
ADDITIONAL DESIGN REQUIREMENTS 237 8.4 DESIGN OF THE FULLY-DIFFERENTIAL
HIGH-GAIN AMPLIFIER 238 8.4.1 EQUIVALENT OUTPUT LOAD 240 8.4.2
PROCEDURAL DESIGN SEQUENCE 241 8.4.3 SIMULATION RESULTS 248 8.5 DESIGN
OF THE FULLY-DIFFERENTIAL DIFFERENCE AMPLIFIER 251 8.5.1 PROCEDURAL
DESIGN SEQUENCE 253 8.5.2 SIMULATION RESULTS 263 8.6 DESIGN OF THE
FULLY-DIFFERENTIAL TWO-STAGE AMPLIFIER 267 8.6.1 EQUIVALENT OUTPUT LOAD
267 8.6.2 ADDITIONAL DESIGN REQUIREMENTS FOR THE CONTINUOUS-TIME
INTEGRATOR 270 8.6.3 PROCEDURAL DESIGN SEQUENCE 272 8.6.4 SIMULATION
RESULTS 276 8.7 CONCLUSION 279 BIBLIOGRAPHY 280 INDEX 28 1 XII
|
| any_adam_object | 1 |
| author | Stefanović, Danica Kayal, Maher 1959- |
| author_GND | (DE-588)139721592 (DE-588)139721371 |
| author_facet | Stefanović, Danica Kayal, Maher 1959- |
| author_role | aut aut |
| author_sort | Stefanović, Danica |
| author_variant | d s ds m k mk |
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| bvnumber | BV036057255 |
| classification_rvk | ZN 4960 |
| ctrlnum | (OCoLC)254885502 (DE-599)DNB98817748X |
| dewey-full | 621.39732 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39732 |
| dewey-search | 621.39732 |
| dewey-sort | 3621.39732 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV036057255 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:10:29Z |
| institution | BVB |
| isbn | 9781402085727 1402085729 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018948818 |
| oclc_num | 254885502 |
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| owner | DE-1043 DE-29T |
| owner_facet | DE-1043 DE-29T |
| physical | 350 S. Ill., graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Springer |
| record_format | marc |
| series2 | Analog circuits and signal processing |
| spelling | Stefanović, Danica Verfasser (DE-588)139721592 aut Structured analog CMOS design Danica Stefanovic ; Maher Kayal Berlin [u.a.] Springer 2008 350 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Analog circuits and signal processing Electronic analog computers - Circuits Metal oxide semiconductors, Complementary Kayal, Maher 1959- Verfasser (DE-588)139721371 aut GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018948818&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Stefanović, Danica Kayal, Maher 1959- Structured analog CMOS design Electronic analog computers - Circuits Metal oxide semiconductors, Complementary |
| title | Structured analog CMOS design |
| title_auth | Structured analog CMOS design |
| title_exact_search | Structured analog CMOS design |
| title_full | Structured analog CMOS design Danica Stefanovic ; Maher Kayal |
| title_fullStr | Structured analog CMOS design Danica Stefanovic ; Maher Kayal |
| title_full_unstemmed | Structured analog CMOS design Danica Stefanovic ; Maher Kayal |
| title_short | Structured analog CMOS design |
| title_sort | structured analog cmos design |
| topic | Electronic analog computers - Circuits Metal oxide semiconductors, Complementary |
| topic_facet | Electronic analog computers - Circuits Metal oxide semiconductors, Complementary |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018948818&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT stefanovicdanica structuredanalogcmosdesign AT kayalmaher structuredanalogcmosdesign |