On and off-chip crosstalk avoidance in VLSI design:
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| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
New York u.a.
Springer
2010
|
| Edition: | 1. Aufl. |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | XXIV, 240 S. 235 mm x 155 mm |
| ISBN: | 9781441909466 |
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MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV036018132 | ||
| 003 | DE-604 | ||
| 005 | 20100312 | ||
| 007 | t | ||
| 008 | 100209s2010 gw |||| 00||| eng d | ||
| 015 | |a 09,N23,1501 |2 dnb | ||
| 016 | 7 | |a 994283695 |2 DE-101 | |
| 020 | |a 9781441909466 |c GB. : EUR 106.95 (freier Pr.), ca. sfr 165.00 (freier Pr.) |9 978-1-441-90946-6 | ||
| 024 | 3 | |a 9781441909466 | |
| 028 | 5 | 2 | |a 12664276 |
| 035 | |a (OCoLC)463639459 | ||
| 035 | |a (DE-599)DNB994283695 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 044 | |a gw |c XA-DE-BE | ||
| 049 | |a DE-91 | ||
| 050 | 0 | |a TK7874.75 | |
| 082 | 0 | |a 621.395 |2 22 | |
| 084 | |a ELT 355f |2 stub | ||
| 084 | |a 380 |2 sdnb | ||
| 100 | 1 | |a Duan, Chunjie |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a On and off-chip crosstalk avoidance in VLSI design |c Chunjie Duan ; Brock LaMeres ; Sunil P. Khatri |
| 246 | 1 | 3 | |a On and off chip crosstalk avoidance in VLSI-design |
| 250 | |a 1. Aufl. | ||
| 264 | 1 | |a New York u.a. |b Springer |c 2010 | |
| 300 | |a XXIV, 240 S. |c 235 mm x 155 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Crosstalk |x Prevention | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design | |
| 700 | 1 | |a LaMeres, Brock J. |e Verfasser |4 aut | |
| 700 | 1 | |a Khatri, Sunil P. |e Verfasser |4 aut | |
| 856 | 4 | 2 | |m SWB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018910309&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-018910309 | ||
Record in the Search Index
| _version_ | 1804141044683505664 |
|---|---|
| adam_text | IMAGE 1
CONTENTS
PART I ON-CHIP CROSSTALK AND AVOIDANCE . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 1
1 INTRODUCTION OF ON-CHIP CROSSTALK AVOIDANCE . . . . . . . . . . . . .
. . . . . . . . 3
1.1 CHALLENGES IN DEEP SUBMICRON PROCESSES . . . . . . . . . . . . . . .
. . . . . . . 3
1.2 OVERVIEW OF ON-CHIP CROSSTALK AVOIDANCE . . . . . . . . . . . . . .
. . . . . . 4
1.3 BUS ENCODING FOR CROSSTALK AVOIDANCE . . . . . . . . . . . . . . . .
. . . . . . . . 9
1.4 PART I ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 10
2 PRELIMINARIES TO ON-CHIP CROSSTALK . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 13
2.1 MODELING OF ON-CHIP INTERCONNECTS . . . . . . . . . . . . . . . . .
. . . . . . . . . 13
2.2 CROSSTALK BASED BUS CLASSIFICATION . . . . . . . . . . . . . . . . .
. . . . . . . . . . 22
2.3 BUS ENCODING FOR CROSSTALK AVOIDANCE . . . . . . . . . . . . . . . .
. . . . . . . . 24
2.4 NOTATION AND TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 25
3 MEMORYLESS CROSSTALK AVOIDANCE CODES . . . . . . . . . . . . . . . . .
. . . . . . . . . 27
3.1 3C-FREE CACS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 27
3.1.1 FORBIDDEN PATTERN FREE CAC . . . . . . . . . . . . . . . . . . . .
. . . . . . 28
3.1.2 FORBIDDEN TRANSITION FREE CAC . . . . . . . . . . . . . . . . . .
. . . . . 32
3.1.3 CIRCUIT IMPLEMENTATION AND SIMULATION RESULTS . . . . . . . . . .
35 3.2 2C-FREE CACS . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 37
3.2.1 CODE CONSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 38
3.2.2 CODE CARDINALITY AND AREA OVERHEAD . . . . . . . . . . . . . . . .
. . . 40
3.2.3 2C EXPERIMENTS . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 42
3.3 1C-FREE BUSSES . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 42
3.3.1 BUS CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 43
3.3.2 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 43
3.4 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 44
4 CODEC DESIGNS FOR MEMORYLESS CROSSTALK AVOIDANCE CODES . . . . . . .
47 4.1 BUS PARTITIONING BASED CODEC DESIGN TECHNIQUES . . . . . . . . .
. . . . 47
4.2 GROUP COMPLEMENT . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 48
4.2.1 PROOF OF CORRECTNESS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 50
4.3 BIT OVERLAPPING . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 51
IX
IMAGE 2
X CONTENTS
4.4 FPF-CAC CODEC DESIGN . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 51
4.4.1 FIBONACCI-BASED BINARY NUMERAL SYSTEM . . . . . . . . . . . . . .
. 52
4.4.2 NEAR-OPTIMAL CODEC . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . 53
4.4.3 OPTIMAL CODEC . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 57
4.4.4 IMPLEMENTATION AND EXPERIMENTAL RESULTS . . . . . . . . . . . . .
. . 59
4.5 FTF-CAC CODEC DESIGN . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 65
4.5.1 MAPPING SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 65
4.5.2 CODING ALGORITHM . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 66
4.5.3 IMPLEMENTATION AND EXPERIMENTAL RESULTS . . . . . . . . . . . . .
. . 67
4.6 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 70
5 MEMORY-BASED CROSSTALK AVOIDANCE CODES . . . . . . . . . . . . . . . .
. . . . . . . . 73
5.1 A 4C-FREE CAC . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 73
5.1.1 A 4C-FREE ENCODING TECHNIQUE . . . . . . . . . . . . . . . . . . .
. . . . . 73
5.1.2 AN EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 74
5.2 CODEWORD GENERATION BY PRUNING . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 75
5.3 CODEWORD GENERATION USING ROBDD . . . . . . . . . . . . . . . . . .
. . . . . . . 80
5.3.1 EFFICIENT CONSTRUCTION OF G KC * FREE M . . . . . . . . . . . . .
. . . . . . . . . 80
5.3.2 AN EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 82
5.3.3 FINDING THE EFFECTIVE KC FREE BUS WIDTH FROM G KC * FREE M . . . .
83
5.3.4 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 84
5.4 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 85
6 MULTI-VALUED LOGIC CROSSTALK AVOIDANCE CODES . . . . . . . . . . . . .
. . . . . . . 87
6.1 BUS CLASSIFICATION IN MULTI-VALUED BUSSES . . . . . . . . . . . . .
. . . . . . . . 88
6.2 LOW POWER AND CROSSTALK AVOIDING CODING ON A TERNARY BUS . . . . .
90 6.2.1 DIRECT BINARY-TERNARY MAPPING . . . . . . . . . . . . . . . . .
. . . . . . 90
6.2.2 4X TERNARY CODE . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 91
6.2.3 3X TERNARY CODE . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 93
6.3 CIRCUIT IMPLEMENTATIONS . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 94
6.4 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 95
6.5 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 98
7 SUMMARY OF ON-CHIP CROSSTALK AVOIDANCE . . . . . . . . . . . . . . . .
. . . . . . . . 101
PART II OFF-CHIP CROSSTALK AND AVOIDANCE . . . . . . . . . . . . . . . .
. . . . . . . . . . . 105
8 INTRODUCTION TO OFF-CHIP CROSSTALK . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 107
8.1 THE ROLE OF IC PACKAGING . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 107
8.2 NOISE SOURCES IN PACKAGING . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 109
8.2.1 INDUCTIVE SUPPLY BOUNCE . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 109
8.2.2 INDUCTIVE SIGNAL COUPLING . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 111
8.2.3 CAPACITIVE BANDWIDTH LIMITING . . . . . . . . . . . . . . . . . .
. . . . . . 113
8.2.4 CAPACITIVE SIGNAL COUPLING . . . . . . . . . . . . . . . . . . . .
. . . . . . . 114
8.2.5 IMPEDANCE DISCONTINUITIES . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 115
IMAGE 3
CONTENTS XI
8.3 PERFORMANCE MODELING AND PROPOSED TECHNIQUES . . . . . . . . . . . .
. . . 117
8.3.1 PERFORMANCE MODELING . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 117
8.3.2 OPTIMAL BUS SIZING . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 117
8.3.3 BUS ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 118
8.3.4 IMPEDANCE COMPENSATION . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 119
8.4 ADVANTAGES OVER PRIOR TECHNIQUES . . . . . . . . . . . . . . . . . .
. . . . . . . . . 120
8.4.1 PERFORMANCE MODELING . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 120
8.4.2 OPTIMAL BUS SIZING . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 121
8.4.3 BUS ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 122
8.4.4 IMPEDANCE COMPENSATION . . . . . . . . . . . . . . . . . . . . . .
. . . . . . 123
8.5 BROADER IMPACT OF THIS MONOGRAPH . . . . . . . . . . . . . . . . . .
. . . . . . . . . 123
8.6 ORGANIZATION OF PART II OF THIS MONOGRAPH . . . . . . . . . . . . .
. . . . . . . . 124
9 PACKAGE CONSTRUCTION AND ELECTRICAL MODELING . . . . . . . . . . . . .
. . . . . . . 125
9.1 LEVEL 1 INTERCONNECT . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 125
9.1.1 WIRE BONDING . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 125
9.1.2 FLIP-CHIP BUMPING . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 127
9.2 LEVEL 2 INTERCONNECT . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 129
9.2.1 LEAD FRAME . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 129
9.2.2 ARRAY PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 130
9.3 MODERN PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 131
9.3.1 QUAD FLAT PACK WITH WIRE BONDING . . . . . . . . . . . . . . . . .
. . . . 132
9.3.2 BALL GRID ARRAY WITH WIRE BONDING . . . . . . . . . . . . . . . .
. . . . 133
9.3.3 BALL GRID ARRAY WITH FLIP-CHIP BUMPING . . . . . . . . . . . . . .
. . 134
9.4 ELECTRICAL MODELING . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 135
9.4.1 QUAD FLAT PACK WITH WIRE BONDING . . . . . . . . . . . . . . . . .
. . . . 135
9.4.2 BALL GRID ARRAY WITH WIRE BONDING . . . . . . . . . . . . . . . .
. . . . 135
9.4.3 BALL GRID ARRAY WITH FLIP-CHIP BUMPING . . . . . . . . . . . . . .
. . 136
10 PRELIMINARIES AND TERMINOLOGY . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 137
10.1 BUS CONSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 137
10.2 LOGIC VALUES AND TRANSITIONS . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 139
10.3 SIGNAL COUPLING . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 140
10.3.1 MUTUAL INDUCTIVE SIGNAL COUPLING . . . . . . . . . . . . . . . .
. . . . . 140
10.3.2 MUTUAL CAPACITIVE SIGNAL COUPLING . . . . . . . . . . . . . . . .
. . . . 141
10.4 RETURN CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 141
10.5 NOISE LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 142
11 ANALYTICAL MODEL FOR OFF-CHIP BUS PERFORMANCE . . . . . . . . . . . .
. . . . . . . 145
11.1 PACKAGE PERFORMANCE METRICS . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 145
11.2 CONVERTING PERFORMANCE TO RISETIME . . . . . . . . . . . . . . . .
. . . . . . . . . . 146
11.3 CONVERTING BUS PERFORMANCE TO DI DT AND DV DT . . . . . . . . . . .
. . . . . . . . . . . 147
11.4 TRANSLATING NOISE LIMITS TO PERFORMANCE . . . . . . . . . . . . . .
. . . . . . . . 148
11.4.1 INDUCTIVE SUPPLY BOUNCE . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 148
11.4.2 CAPACITIVE BANDWIDTH LIMITING . . . . . . . . . . . . . . . . . .
. . . . . . 150
IMAGE 4
XII CONTENTS
11.4.3 SIGNAL COUPLING . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 151
11.4.4 IMPEDANCE DISCONTINUITIES . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 152
11.5 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 152
11.5.1 TEST CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 153
11.5.2 QUAD FLAT PACK WITH WIRE BONDING RESULTS . . . . . . . . . . . .
. . 154
11.5.3 BALL GRID ARRAY WITH WIRE BONDING RESULTS . . . . . . . . . . . .
. . 156
11.5.4 BALL GRID ARRAY WITH FLIP-CHIP BUMPING RESULTS . . . . . . . . .
157 11.5.5 DISCUSSION . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 159
12 OPTIMAL BUS SIZING . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 161
12.1 PACKAGE COST . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 161
12.2 BANDWIDTH PER COST . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 163
12.2.1 RESULTS FOR QUAD FLAT PACK WITH WIRE BONDING . . . . . . . . . .
. 163 12.2.2 RESULTS FOR BALL GRID ARRAY WITH WIRE BONDING . . . . . . .
. . . . 164 12.2.3 RESULTS FOR BALL GRID ARRAY WITH FLIP-CHIP BUMPING .
. . . . . 164 12.3 BUS SIZING EXAMPLE . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . 166
13 BUS EXPANSION ENCODER . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . 167
13.1 CONSTRAINT EQUATIONS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 167
13.1.1 SUPPLY BOUNCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . .
. . . . . . . 168
13.1.2 SIGNAL COUPLING CONSTRAINTS . . . . . . . . . . . . . . . . . . .
. . . . . . . 168
13.1.3 CAPACITIVE BANDWIDTH LIMITING CONSTRAINTS . . . . . . . . . . . .
. 170 13.1.4 IMPEDANCE DISCONTINUITY CONSTRAINTS . . . . . . . . . . . .
. . . . . . . 171
13.1.5 NUMBER OF CONSTRAINT EQUATIONS . . . . . . . . . . . . . . . . .
. . . . . . 172
13.1.6 NUMBER OF CONSTRAINT EVALUATIONS . . . . . . . . . . . . . . . .
. . . . . 172
13.2 ENCODER CONSTRUCTION . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 173
13.2.1 ENCODER ALGORITHM . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 173
13.2.2 ENCODER OVERHEAD . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 175
13.3 DECODER CONSTRUCTION . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 175
13.4 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 175
13.4.1 3-BIT FIXED DI DT EXAMPLE . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 176
13.4.2 3-BIT VARYING DI DT EXAMPLE . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 180
13.4.3 FUNCTIONAL IMPLEMENTATION . . . . . . . . . . . . . . . . . . . .
. . . . . . . 182
13.4.4 PHYSICAL IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 183
13.4.5 MEASUREMENT RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 185
14 BUS STUTTERING ENCODER . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 189
14.1 ENCODER CONSTRUCTION . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 189
14.1.1 ENCODER ALGORITHM . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 190
14.1.2 ENCODER OVERHEAD . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . 191
14.2 DECODER CONSTRUCTION . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 192
14.3 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 192
14.3.1 FUNCTIONAL IMPLEMENTATION . . . . . . . . . . . . . . . . . . . .
. . . . . . . 194
14.3.2 PHYSICAL IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 196
IMAGE 5
CONTENTS XIII
14.3.3 MEASUREMENT RESULTS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . 197
14.3.4 DISCUSSION . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . 198
15 IMPEDANCE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 201
15.1 STATIC COMPENSATOR . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . 202
15.1.1 METHODOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 202
15.1.2 COMPENSATOR PROXIMITY . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 203
15.1.3 ON-CHIP CAPACITORS . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 203
15.1.4 ON-PACKAGE CAPACITORS . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 205
15.1.5 STATIC COMPENSATOR DESIGN . . . . . . . . . . . . . . . . . . . .
. . . . . . . 205
15.1.6 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 207
15.2 DYNAMIC COMPENSATOR . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 210
15.2.1 METHODOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 210
15.2.2 DYNAMIC COMPENSATOR DESIGN . . . . . . . . . . . . . . . . . . .
. . . . . 210
15.2.3 EXPERIMENTAL RESULTS . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 213
15.2.4 DYNAMIC COMPENSATOR CALIBRATION . . . . . . . . . . . . . . . . .
. . . . 216
16 FUTURE TRENDS AND APPLICATIONS . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 219
16.1 THE MOVE FROM ASICS TO FPGAS . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 219
16.2 IP CORES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . 222
16.3 POWER MINIMIZATION . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . 223
16.4 CONNECTORS AND BACKPLANES . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . 224
16.5 INTERNET FABRIC . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . 225
17 SUMMARY OF OFF-CHIP CROSSTALK AVOIDANCE . . . . . . . . . . . . . . .
. . . . . . . . 227
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . 231
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 239
|
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| author | Duan, Chunjie LaMeres, Brock J. Khatri, Sunil P. |
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| id | DE-604.BV036018132 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T22:09:37Z |
| institution | BVB |
| isbn | 9781441909466 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018910309 |
| oclc_num | 463639459 |
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| owner_facet | DE-91 DE-BY-TUM |
| physical | XXIV, 240 S. 235 mm x 155 mm |
| publishDate | 2010 |
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| publisher | Springer |
| record_format | marc |
| spelling | Duan, Chunjie Verfasser aut On and off-chip crosstalk avoidance in VLSI design Chunjie Duan ; Brock LaMeres ; Sunil P. Khatri On and off chip crosstalk avoidance in VLSI-design 1. Aufl. New York u.a. Springer 2010 XXIV, 240 S. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Crosstalk Prevention Integrated circuits Very large scale integration Design LaMeres, Brock J. Verfasser aut Khatri, Sunil P. Verfasser aut SWB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018910309&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Duan, Chunjie LaMeres, Brock J. Khatri, Sunil P. On and off-chip crosstalk avoidance in VLSI design Crosstalk Prevention Integrated circuits Very large scale integration Design |
| title | On and off-chip crosstalk avoidance in VLSI design |
| title_alt | On and off chip crosstalk avoidance in VLSI-design |
| title_auth | On and off-chip crosstalk avoidance in VLSI design |
| title_exact_search | On and off-chip crosstalk avoidance in VLSI design |
| title_full | On and off-chip crosstalk avoidance in VLSI design Chunjie Duan ; Brock LaMeres ; Sunil P. Khatri |
| title_fullStr | On and off-chip crosstalk avoidance in VLSI design Chunjie Duan ; Brock LaMeres ; Sunil P. Khatri |
| title_full_unstemmed | On and off-chip crosstalk avoidance in VLSI design Chunjie Duan ; Brock LaMeres ; Sunil P. Khatri |
| title_short | On and off-chip crosstalk avoidance in VLSI design |
| title_sort | on and off chip crosstalk avoidance in vlsi design |
| topic | Crosstalk Prevention Integrated circuits Very large scale integration Design |
| topic_facet | Crosstalk Prevention Integrated circuits Very large scale integration Design |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018910309&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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