High performance embedded architectures and compilers: 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings
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| Format: | Conference Proceeding Book |
|---|---|
| Language: | English |
| Published: |
Berlin [u.a.]
Springer
2010
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| Series: | Lecture notes in computer science
5952 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Literaturangaben |
| Physical Description: | XIII, 370 S. graph. Darst. 24 cm |
| ISBN: | 9783642115141 |
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TABLE OF CONTENTS INVITED PROGRAM EMBEDDED SYSTEMS AS DATACENTERS
(KEYNOTE) 1 BOB IANNUCCI LARRABEE: A MANY-CORE INTEL ARCHITECTURE FOR
VISUAL COMPUTING (KEYNOTE) 2 ROGER ESPASA ARCHITECTURAL SUPPORT FOR
CONCURRENCY REMOTE STORE PROGRAMMING: A MEMORY MODEL FOR EMBEDDED
MULTICORE 3 HENRY HOFFMANN, DAVID WENTZLAFF, AND ANANT AGARWAL
LOW-OVERHEAD, HIGH-SPEED MULTI-CORE BARRIER SYNCHRONIZATION 18 JOHN
SARTORI AND RAKESH KUMAR IMPROVING PERFORMANCE BY REDUCING ABORTS IN
HARDWARE TRANSACTIONAL MEMORY 35 MOHAMMAD ANSARI, BEHRAM KHAN, MIKEL
LUJDN, CHRISTOS KOTSELIDIS, CHRIS KIRKHAM, AND IAN WATSON ENERGY AND
THROUGHPUT EFFICIENT TRANSACTIONAL MEMORY FOR EMBEDDED MULTICORE SYSTEMS
50 CESARE FERRI, SAMANTHA WOOD, TALI MORESHET, IRIS BAHAR, AND MAURICE
HERLIHY COMPILATION AND RUNTIME SYSTEMS SPLIT REGISTER ALLOCATION:
LINEAR COMPLEXITY WITHOUT THE PERFORMANCE PENALTY 66 BOUBACAR DIOUF,
ALBERT COHEN, FABRICE RASTELLO, AND JOHN CAVAZOS TRACE-BASED DATA LAYOUT
OPTIMIZATIONS FOR MULTI-CORE PROCESSORS 81 OLGA GOLOVANEVSKY, ALAN
DAYAN, AYAL ZAKS, AND DAVID EDELSVHN BUFFER SIZING FOR SELF-TIMED STREAM
PROGRAMS ON HETEROGENEOUS DISTRIBUTE BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/998955736 DIGITALISIERT DURCH RECONFIGURABLE AND
CUSTOMIZED ARCHITECTURES VIRTUAL WAYS: EFFICIENT COHERENCE FOR
ARCHITECTURALLY VISIBLE STORAGE IN AUTOMATIC INSTRUCTION SET EXTENSIONS
126 THEO KLUTER, SAMUEL BURRI, PHILIP BRISK, EDOARDO CHARBON, AND PAOLO
IENNE ACCELERATING XML QUERY MATCHING THROUGH CUSTOM STACK GENERATION ON
FPGAS 141 ROGER MOUSSALLI, MARIAM SALLOUM, WALID NAJJAR, AND VASSILIS
TSOTRAS AN APPLICATION-AWARE LOAD BALANCING STRATEGY FOR NETWORK
PROCESSORS 156 RAINER OHLENDORF, MICHAEL MEUEINGER, THOMAS WILD, AND
ANDREAS HERKERSDORF MEMORY-AWAERE APPLICATION MAPPING ON COARSE-GRAINED
RECONFIGURABLE ARRAYS 171 YONGJOO KIM, JONGEUN LEE, AVIRAL SHRIVASTAVA,
JONGHEE YOON, AND YUNHEUNG PAEK MULTICORE EFFICIENCY, RELIABILITY, AND
POWER MAESTRO: ORCHESTRATING LIFETIME RELIABILITY IN CHIP
MULTIPROCESSORS . 186 SHUGUANG FENG, SHANTANU GUPTA, AMIN ANSARI, AND
SCOTT MAHLKE COMBINING LOCALITY ANALYSIS WITH ONLINE PROACTIVE JOB
CO-SCHEDULING IN CHIP MULTIPROCESSORS 201 YUNLIAN JIANG, KAI TIAN, AND
XIPENG SHEN RELOCATE: REGISTER FILE LOCAL ACCESS PATTERN REDISTRIBUTION
MECHANISM FOR POWER AND THERMAL MANAGEMENT IN OUT-OF-ORDER EMBEDDED
PROCESSOR 216 HOUMAN HOMAYOUN, ASEEM GUPTA, ALEX VEIDENBAUM, AVESTA
SASAN (M.A. MAKHZAN), FADI KURDAHI, AND NIKIL DUTT PERFORMANCE AND POWER
AWARE CMP THREAD ALLOCATION MODELING 232 YANIV SRP: SYMBIOTIC RESOURCE
PARTITIONING OF THE MEMORY HIERARCHY IN CMPS 277 SHEKHAR SRIKANTAIAH AND
MAHMUT KANDEMIR DIEF: AN ACCURATE INTERFERENCE FEEDBACK MECHANISM FOR
CHIP MULTIPROCESSOR MEMORY SYSTEMS 292 MAGNUS JAHRE, MARIUS GRANNAES,
AND LASSE NATVIG PROGRAMMING AND ANALYSIS OF ACCELERATORS TAGGED
PROCEDURE CALLS (TPC): EFFICIENT RUNTIME SUPPORT FOR TASK-BASED
PARALLELISM ON THE CELL PROCESSOR 307 GEORGE TZENAKIS, KONSTANTINOS
KAPELONIS, MICHAIL ALVANOS, KONSTANTINOS KOUKOS, DIMUERIOS S.
NIKOLOPOULOS, AND ANGELOS BILAS ANALYSIS OF TASK OFFLOADING FOR
ACCELERATORS 322 ROGER FERNER, VICENC BEITRAN, MARC GONZALEZ, XAVIER
MARTORELL, AND EDUARD AYGUADE OFFLOAD AUTOMATING CODE MIGRATION TO
HETEROGENEOUS MULTICORE SYSTEMS 337 PETE COOPER, UWE DOLINSKY, ALASTAIR
F. DONALDSON, ANDREW RICHARDS, COLIN RILEY, AND GEORGE RUSSELL COMPUTER
GENERATION OF EFFICIENT SOFTWARE VITERBI DECODERS 353 FREDERIC DE
MESMAY, SRINIVAS CHELLAPPA, FRANZ FRANCHETTI, AND MARKUS PUESCHEL AUTHOR
INDEX 369 |
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| dewey-full | 004.3 |
| dewey-hundreds | 000 - Computer science, information, general works |
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| dewey-raw | 004.3 |
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| discipline | Informatik |
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| spelling | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings Yale N. Patt ... (ed.) Berlin [u.a.] Springer 2010 XIII, 370 S. graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 5952 Literaturangaben Compiler (DE-588)4148248-7 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Supercomputer (DE-588)4128144-5 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2010 Pisa gnd-content Eingebettetes System (DE-588)4396978-1 s Computerarchitektur (DE-588)4048717-9 s Compiler (DE-588)4148248-7 s DE-604 Supercomputer (DE-588)4128144-5 s Patt, Yale 1939- Sonstige (DE-588)1079568301 oth HiPEAC 5 2010 Pisa Sonstige (DE-588)16054240-6 oth Lecture notes in computer science 5952 (DE-604)BV000000607 5952 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018881203&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings Lecture notes in computer science Compiler (DE-588)4148248-7 gnd Computerarchitektur (DE-588)4048717-9 gnd Eingebettetes System (DE-588)4396978-1 gnd Supercomputer (DE-588)4128144-5 gnd |
| subject_GND | (DE-588)4148248-7 (DE-588)4048717-9 (DE-588)4396978-1 (DE-588)4128144-5 (DE-588)1071861417 |
| title | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings |
| title_auth | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings |
| title_exact_search | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings |
| title_full | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings Yale N. Patt ... (ed.) |
| title_fullStr | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings Yale N. Patt ... (ed.) |
| title_full_unstemmed | High performance embedded architectures and compilers 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings Yale N. Patt ... (ed.) |
| title_short | High performance embedded architectures and compilers |
| title_sort | high performance embedded architectures and compilers 5th international conference hipeac 2010 pisa italy january 25 27 2010 proceedings |
| title_sub | 5th international conference, HiPEAC 2010, Pisa, Italy, January 25 - 27, 2010 ; proceedings |
| topic | Compiler (DE-588)4148248-7 gnd Computerarchitektur (DE-588)4048717-9 gnd Eingebettetes System (DE-588)4396978-1 gnd Supercomputer (DE-588)4128144-5 gnd |
| topic_facet | Compiler Computerarchitektur Eingebettetes System Supercomputer Konferenzschrift 2010 Pisa |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018881203&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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