Wu, K. (1979). Synthesis of accurate and efficient functional modelling techniques for performing design verification of very large scale integrated digital circuits and systems in a hierarchical digital logic simulation environment ([Mikrofiche-Ausg.].).
Chicago-Zitierstil (17. Ausg.)Wu, Kwok-Wai. Synthesis of Accurate and Efficient Functional Modelling Techniques for Performing Design Verification of Very Large Scale Integrated Digital Circuits and Systems in a Hierarchical Digital Logic Simulation Environment. [Mikrofiche-Ausg.]. 1979.
MLA-Zitierstil (9. Ausg.)Wu, Kwok-Wai. Synthesis of Accurate and Efficient Functional Modelling Techniques for Performing Design Verification of Very Large Scale Integrated Digital Circuits and Systems in a Hierarchical Digital Logic Simulation Environment. [Mikrofiche-Ausg.]. 1979.