FPGAs: world class designs
Saved in:
| Format: | Book |
|---|---|
| Language: | English |
| Published: |
Amsterdam [u.a.]
Elsevier, Newnes
2009
|
| Series: | Newnes world class designs series
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Item Description: | Includes bibliographical references and index |
| Physical Description: | XIX, 452, 12 S. graph. Darst. |
| ISBN: | 9781856176217 1856176215 |
Staff View
MARC
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| 020 | |a 9781856176217 |c pbk. |9 978-1-85617-621-7 | ||
| 020 | |a 1856176215 |c pbk. |9 1-85617-621-5 | ||
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| 245 | 1 | 0 | |a FPGAs |b world class designs |c Clive "Max" Maxfield [editor] ; with W. Bolton ... [et al.] |
| 264 | 1 | |a Amsterdam [u.a.] |b Elsevier, Newnes |c 2009 | |
| 300 | |a XIX, 452, 12 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Newnes world class designs series | |
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Field programmable gate arrays | |
| 650 | 4 | |a Field programmable gate arrays |x Design and construction | |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Maxfield, Clive |e Sonstige |4 oth | |
| 700 | 1 | |a Bolton, William |d 1933- |e Sonstige |0 (DE-588)171983378 |4 oth | |
| 856 | 4 | 2 | |m Digitalisierung UB Bayreuth |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017687970&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-017687970 | ||
Record in the Search Index
| _version_ | 1804139310034714624 |
|---|---|
| adam_text | Contents
Preface
...............................................................................................
їх
About the Editor
.................................................................................xv
About the Contributors
........................................................................xvii
Chapter
1:
Alternative FPGA Architectures
.............................................. 1
1.1
A Word of Warning
..............................................................................2
1.2
A Little Background Information
..........................................................2
1.3
Antifuse
versus SRAM versus
............................................................4
1.4
Fine-, Medium-, and Coarse-Grained Architectures
.............................11
1.5
MUX- versus LUT-Based Logic Blocks
..............................................12
1.6
CLBs versus LABs versus Slices
........................................................18
1.7
Fast Carry Chains
...............................................................................22
1.8
Embedded RAMs
...............................................................................23
1.9
Embedded Multipliers, Adders, MACs, Etc
.........................................24
1.10
Embedded Processor Cores (Hard and Soft)
........................................25
1.11
Clock Trees and Clock Managers
.......................................................29
1.12
General-Purpose I/O
...........................................................................34
1.13
Gigabit Transceivers
...........................................................................37
1.14
Hard IP, Soft IP, and Firm IP
.............................................................38
1.15
System Gates versus Real Gates
.........................................................40
1.16
FPGA Years
.......................................................................................43
Chapter
2:
Design Techniques, Rules, and Guidelines
...............................45
2.1
Hardware Description Languages
........................................................47
2.2
Top-Down Design
..............................................................................65
2.3
Synchronous Design
...........................................................................69
2.4
Floating Nodes
...................................................................................87
2.5
Bus Contention
...................................................................................88
2.6
One-Hot State Encoding
.....................................................................90
www.newnespress.com
vi
Contents
2.7
Design
For
Test (DFT)
.......................................................................92
2.8
Testing Redundant
Logic
....................................................................94
2.9
Initializing
State Machines
..................................................................96
2.10
Observable Nodes...............................................................................
97
2.11
Scan Techniques
.................................................................................98
2.12
Built-in Self-Test (BIST)
..................................................................100
2.13
Signature Analysis
............................................................................102
2.14
Summary
..........................................................................................103
Chapters: A VHDL Primer: The Essentials
..........................................107
3.1
Introduction
......................................................................................108
3.2
Entity: Model Interface
.....................................................................109
3.3
Architecture: Model Behavior
...........................................................112
3.4
Process: Basic Functional Unit in VHDL
..........................................114
3.5
Basic Variable Types and Operators
..................................................115
3.6
Decisions and Loops
.........................................................................118
3.7
Hierarchical Design
..........................................................................123
3.8
Debugging Models
............................................................................127
3.9
Basic Data Types
..............................................................................127
3.10
Summary
..........................................................................................130
Chapter
4:
Modeling Memories
...........................................................131
4.1
Memory Arrays
................................................................................132
4.2
Modeling Memory Functionality
.......................................................135
4.3
VITAL_Memory Path Delays
...........................................................168
4.4
VITAL_Memory Timing Constraints
.................................................172
4.5
Preloading Memories
........................................................................172
4.6
Modeling Other Memory Types
........................................................177
4.7
Summary
..........................................................................................193
Chapter
5:
Introduction to Synchronous State Machine
Desigp and Analysis
...........................................................................195
5.1
Introduction
......................................................................................196
5.2
Models for Sequential Machines
.......................................................199
5.3
The Fully Documented State Diagram
...............................................203
5.4
The Basic Memory Cells
..................................................................207
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Contents
vii
5.5
Introduction
to
Flip-Flops.................................................................218
5.6
Procedure for FSM
(Flip-Flop)
Design and the Mapping Algorithm
.....222
5.7
The
D
Flip-Flops: General
................................................................223
5.8
Flip-Flop Conversion: The T,
Ж
Flip-Flops
and Miscellaneous
Rip-Flops
.........................................................................................235
5.9
Latches and Flip-Flops with Serious Timing Problems: A Warning
......248
5.10
Asynchronous Preset and Clear Overrides
.........................................250
5.11
Setup and Hold Time Requirements of Flip-Flops
.............................252
5.12
Design of Simple Synchronous State Machines with
Edge-Triggered Flip-Flops: Map Conversion
.....................................253
5.13
Analysis of Simple State Machines
...................................................265
5.14
VHDL Description of Simple State Machines
...................................268
References
.................................................................................................273
Chapter
6:
Embedded Processors
.........................................................275
6.1
Introduction
......................................................................................276
6.2
A Simple Embedded Processor
.........................................................276
6.3
Soft Core Processors on an FPGA
.....................................................303
6.4
Summary
..........................................................................................304
Chapter
7:
Digital Signal Processing
.....................................................305
7.1
Overview
..........................................................................................306
7.2
Basic DSP System
............................................................................307
7.3
Essential DSP Terms
........................................................................308
7.4
DSP Architectures
............................................................................308
7.5
Parallel Execution in DSP Components
.............................................312
7.6
Parallel Execution in FPGA
..............................................................313
7.7
When to Use FPGAs for DSP
...........................................................316
7.8
FPGA DSP Design Considerations
....................................................317
7.9
FIR Filter Concept Example
.............................................................320
7.10
Summary
..........................................................................................322
Chapter
8:
Basics of Embedded Audio Processing
....................................325
8.1
Introduction
......................................................................................326
8.2
Audio Sources and Sinks
..................................................................329
8.3
Interconnections
................................................................................337
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es
press, com
viii Contents
8.4
Dynamic Range and Precision
...........................................................338
8.5
Audio Processing Methods
................................................................349
References
.................................................................................................363
Chapter
9:
Basics of Embedded Video and Image Processing
.....................365
9.1
Introduction
......................................................................................366
9.2
Broadcast TV—NTSC and PAL
........................................................369
9.3
Color Spaces
....................................................................................372
9.4
Digital Video
....................................................................................378
9.5
A Systems View of Video
................................................................383
9.6
Embedded Video Processing Considerations
......................................395
9.7
Compression/Decompression
.............................................................416
References
.................................................................................................427
Chapter
10:
Programming Streaming
F PC A
Applications Using
Block Diagrams in Simulink
.................................................................429
10.1
Designing High-Performance Datapaths using
Stream-Based Operators
....................................................................431
10.2
An Image-Processing Design Driver
.................................................432
10.3
Specifying Control in Simulink
.........................................................442
10.4
Component Reuse: Libraries of Simple and Complex Subsystems
.....447
10.5
Summary
..........................................................................................450
References
.................................................................................................452
Additional chapters
11
and
12
are available on line at www.elsevierdirect.com/
companions/978
1856176217
Chapter
11:
Ladder and Functional Block Programming
Chapter
12:
Timers
Index.
...............................................................................................
¡.ι
www. new
η
es
press,
co
m
|
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| id | DE-604.BV035633071 |
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| indexdate | 2024-07-09T21:42:03Z |
| institution | BVB |
| isbn | 9781856176217 1856176215 |
| language | English |
| lccn | 2009417828 |
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| physical | XIX, 452, 12 S. graph. Darst. |
| publishDate | 2009 |
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| publisher | Elsevier, Newnes |
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| series2 | Newnes world class designs series |
| spelling | FPGAs world class designs Clive "Max" Maxfield [editor] ; with W. Bolton ... [et al.] Amsterdam [u.a.] Elsevier, Newnes 2009 XIX, 452, 12 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Newnes world class designs series Includes bibliographical references and index Field programmable gate arrays Field programmable gate arrays Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Maxfield, Clive Sonstige oth Bolton, William 1933- Sonstige (DE-588)171983378 oth Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017687970&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | FPGAs world class designs Field programmable gate arrays Field programmable gate arrays Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4347749-5 |
| title | FPGAs world class designs |
| title_auth | FPGAs world class designs |
| title_exact_search | FPGAs world class designs |
| title_full | FPGAs world class designs Clive "Max" Maxfield [editor] ; with W. Bolton ... [et al.] |
| title_fullStr | FPGAs world class designs Clive "Max" Maxfield [editor] ; with W. Bolton ... [et al.] |
| title_full_unstemmed | FPGAs world class designs Clive "Max" Maxfield [editor] ; with W. Bolton ... [et al.] |
| title_short | FPGAs |
| title_sort | fpgas world class designs |
| title_sub | world class designs |
| topic | Field programmable gate arrays Field programmable gate arrays Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Field programmable gate arrays Field programmable gate arrays Design and construction Schaltungsentwurf Field programmable gate array |
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