Formal specification and verification of hardware: a comparative case study
Abstract: "Formal methods are applied with increased frequency in the specification and verification of digital systems as an alternative to traditional methods of establishing correctness, such as simulation and testing. This article briefly outlines the goals and the philosophy of the HArdwar...
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| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Manchester
Univ.
1987
|
| Series: | Technical report series / University of Manchester, Department of Computer Science.
|
| Subjects: | |
| Summary: | Abstract: "Formal methods are applied with increased frequency in the specification and verification of digital systems as an alternative to traditional methods of establishing correctness, such as simulation and testing. This article briefly outlines the goals and the philosophy of the HArdware VErification project at the Department of Computer Science within the University of Manchester. Our objective here is to report on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems Our strategy consists of working with incrementally harder' test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device. |
| Physical Description: | 17 S. graph. Darst. |
Staff View
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| 246 | 1 | 3 | |a Reportnr. UMCS 87 11 1 |
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| 490 | 0 | |a Technical report series / University of Manchester, Department of Computer Science. | |
| 520 | 3 | |a Abstract: "Formal methods are applied with increased frequency in the specification and verification of digital systems as an alternative to traditional methods of establishing correctness, such as simulation and testing. This article briefly outlines the goals and the philosophy of the HArdware VErification project at the Department of Computer Science within the University of Manchester. Our objective here is to report on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems | |
| 520 | 3 | |a Our strategy consists of working with incrementally harder' test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device. | |
| 650 | 4 | |a Digital integrated circuits |x Verification | |
| 650 | 4 | |a Systems engineering | |
| 700 | 1 | |a Barringer, Howard |e Verfasser |4 aut | |
| 700 | 1 | |a Edwards, Dough A. |e Verfasser |4 aut | |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T21:40:52Z |
| institution | BVB |
| language | English |
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| physical | 17 S. graph. Darst. |
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| series2 | Technical report series / University of Manchester, Department of Computer Science. |
| spelling | Stavridou, Victoria Verfasser aut Formal specification and verification of hardware a comparative case study Reportnr. UMCS 87 11 1 Manchester Univ. 1987 17 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Technical report series / University of Manchester, Department of Computer Science. Abstract: "Formal methods are applied with increased frequency in the specification and verification of digital systems as an alternative to traditional methods of establishing correctness, such as simulation and testing. This article briefly outlines the goals and the philosophy of the HArdware VErification project at the Department of Computer Science within the University of Manchester. Our objective here is to report on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems Our strategy consists of working with incrementally harder' test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device. Digital integrated circuits Verification Systems engineering Barringer, Howard Verfasser aut Edwards, Dough A. Verfasser aut |
| spellingShingle | Stavridou, Victoria Barringer, Howard Edwards, Dough A. Formal specification and verification of hardware a comparative case study Digital integrated circuits Verification Systems engineering |
| title | Formal specification and verification of hardware a comparative case study |
| title_alt | Reportnr. UMCS 87 11 1 |
| title_auth | Formal specification and verification of hardware a comparative case study |
| title_exact_search | Formal specification and verification of hardware a comparative case study |
| title_full | Formal specification and verification of hardware a comparative case study |
| title_fullStr | Formal specification and verification of hardware a comparative case study |
| title_full_unstemmed | Formal specification and verification of hardware a comparative case study |
| title_short | Formal specification and verification of hardware |
| title_sort | formal specification and verification of hardware a comparative case study |
| title_sub | a comparative case study |
| topic | Digital integrated circuits Verification Systems engineering |
| topic_facet | Digital integrated circuits Verification Systems engineering |
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