Transient-induced latchup in CMOS integrated circuits:
"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the c...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Singapore
Wiley [u.a.]
2009
|
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Summary: | "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process." -- Publisher's description. |
| Item Description: | Includes bibliographical references and index Erscheint: Mai 2009 |
| Physical Description: | XIII, 249 S. Ill., graph. Darst. |
| ISBN: | 9780470824078 |
Staff View
MARC
| LEADER | 00000nam a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV035497276 | ||
| 003 | DE-604 | ||
| 005 | 20091110 | ||
| 007 | t | ||
| 008 | 090519s2009 si ad|| |||| 00||| eng d | ||
| 010 | |a 2008045600 | ||
| 020 | |a 9780470824078 |c cloth |9 978-0-470-82407-8 | ||
| 035 | |a (OCoLC)264669592 | ||
| 035 | |a (DE-599)BVBBV035497276 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 044 | |a si |c SG | ||
| 049 | |a DE-703 | ||
| 050 | 0 | |a TK7871.99.M44 | |
| 082 | 0 | |a 621.39/5 | |
| 084 | |a ZN 4960 |0 (DE-625)157426: |2 rvk | ||
| 100 | 1 | |a Ker, Ming-Dou |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Transient-induced latchup in CMOS integrated circuits |c Ming-Dou Ker and Sheng-Fu Hsu |
| 246 | 1 | 3 | |a Transient induced latchup in CMOS integrated circuits |
| 264 | 1 | |a Singapore |b Wiley [u.a.] |c 2009 | |
| 300 | |a XIII, 249 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 500 | |a Erscheint: Mai 2009 | ||
| 520 | 3 | |a "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process." -- Publisher's description. | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Defects | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Reliability | |
| 700 | 1 | |a Hsu, Sheng-Fu |e Verfasser |4 aut | |
| 856 | 4 | 2 | |m Digitalisierung UB Bayreuth |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017553565&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-017553565 | ||
Record in the Search Index
| _version_ | 1804139114365190144 |
|---|---|
| adam_text | Contents
Preface
xi
1
Introduction
1
1.1
Latchup Overview
1
1.2
Background of
TLU
7
1.3
Categories of TLU-Triggering Modes
7
1.3.1
Power-On Transition
7
1.3.2
Transmission Line Reflections
8
1.3.3
Supply Voltage Overshoots
11
1.3.4
Cable Discharge Event
12
1.3.5
System-Level
ESD
Event
13
1.4
TLU
Standard Practice
16
References
19
2
Physical Mechanism of
TLU
under the System-Level
ESD
Test
23
2.1
Background
23
2.2
TLU
in the System-Level
ESD
Test
24
2.3
Test Structure
26
2.4
Measurement Setup
28
2.5
Device Simulation
30
2.5.1
Latchup DC I-V Characteristics
32
2.5.2
Negative Vcharge
32
2.5.3
Positive Vcharge
35
2.5.4
A More Realistic Case
37
2.6
TLU
Measurement
38
2.6.1
Latchup DC I-V Characteristics
38
2.6.2
Negative Vcharge
39
2.6.3
Positive Vcharge
39
2.7
Discussion
41
2.7.1
Dominant Parameter to Induce
TLU
41
2.7.2
Transient Responses on the Minority Carriers Stored
within the SCR
43
Contents
2.8
Conclusion
44
References
44
Component-Level Measurement for
TLU
under System-Level
ESD
Considerations
47
3.1
Background
47
3.2
Component-Level
TLU
Measurement Setup
48
3.3
Influence of the Current-Blocking Diode and Current-Limiting
Resistance on the Bipolar Trigger Waveforms
49
3.3.1
Positive Vcharge 51
3.3.2
Negative Vcharge
51
3.4
Influence of the Current-Blocking Diode and Current-Limiting
Resistance on the
TLU
Level
54
3.4.1
Latchup DC I-V Characteristics
54
3.4.2
Positive
TLU
Level
55
3.4.3
Negative
TLU
Level
57
3.5
Verifications of Device Simulation
59
3.5.1
Dependences of the Current-Blocking Diode on
TLU
Level
59
3.5.2
Dependences of Current-Limiting Resistance on
TLU
Level
62
3.6
Suggested Component-Level
TLU
Measurement Setup
62
3.7
TLU
Verification on Real Circuits
63
3.8
Evaluation on Board-Level Noise Filters to Suppress
TLU
66
3.8.1
TLU
Transient Waveforms of the Ring Oscillator
69
3.8.2
TLU
Level of the Ring Oscillator with Noise Filters
70
3.9
Conclusion
72
References
73
TLU
Dependency on Power-Pin Damping Frequency and Damping
Factor in CMOS Integrated Circuits
75
4.1
Examples of Different
ŰFreq
and Dpactor
ш ше
System-Level
ESD
Test
76
4.2
TLU
Dependency
ОП
Dp«*, and ^Factor
80
4.2.1
Relations between ¿Factor and Minimum Positive
(Negative) Vp to Initiate
TLU
80
4.2.2
Relations between Dp^ and Minimum Positive (Negative)
Vp to Initiate
TLU
82
4.2.3
Relations between Dpactor and Minimum (Maximum) Drreq
to Initiate
TLU
84
4.3
Experimental Verification on
TLU
86
4.4
Suggested Guidelines for
TLU
Prevention
89
4.5
Conclusion
92
References
93
Contents
TLU
in
CMOS ICs in the Electrical Fast Transient Test
95
5.1
Electrical Fast Transient Test
95
5.2 Test
Structure
98
5.3
Experimental Measurements
102
5.3.1
Negative EFT Voltage
103
5.3.2
Positive EFT Voltage
104
5.3.3
Physical Mechanism of
TLU
in the EFT Test
105
5.4
Evaluation on Board-Level Noise Filters to Suppress
TLU
in the EFT Test
106
5.4.1
Capacitor Filter, LC-Like Filter, and
π
-Section
Filter
106
5.4.2
Ferrite
Bead, TVS, and Hybrid Type Filters
109
5.4.3
Discussion 111
5.5.
Conclusion
112
References
112
Methodology on Extracting Compact Layout Rules for
Latchup Prevention
113
6.1
Introduction
113
6.2
Latchup Test
114
6.2.1
Latchup Testing Classification
114
6.2.2
Trigger Current Test
115
6.2.3
VsuppIy Over-Voltage Test
117
6.3
Extraction of Layout Rules for I/O Cells
121
6.3.1
Latchup in I/O Cells
121
6.3.2
Design of Test Structure for I/O Cells
124
6.3.3
Latchup Immunity Dependency of I/O Cells
125
6.4
Extraction of Layout Rules for Internal Circuits
129
6.4.1
Latchup in Internal Circuits
129
6.4.2
Design of Test Structure for Internal Circuits
130
6.4.3
Latchup Immunity Dependency of the Internal Circuits
131
6.5
Extraction of Layout Rules between I/O Cells and
Internal Circuits
136
6.5.1
Layout Considerations between I/O Cells and Internal Circuits
136
6.5.2
Design of Test Structure between I/O Cells and Internal
Circuits
139
6.5.3
Threshold Latchup Trigger Current Dependency
141
6.6
Conclusion
148
References
149
Special Layout Issues for Latchup Prevention
151
7.1
Latchup between Two Different Power Domains
151
7.1.1
Practical Examples
152
7.1.2
Suggested Solutions
156
viii Contents
7.2 Latchup in
Internal Circuits Adjacent to Power-Rail
ESD
Clamp Circuits
156
7.2.1
Practical Examples
157
7.2.2
Suggested Solutions
159
7.3
Unexpected Trigger Point to Initiate Latchup in Internal Circuits
159
7.3.1
Practical Examples
161
7.3.2
Suggested Solutions
165
7.4
Other Unexpected Latchup Paths in CMOS ICs
165
7.5
Conclusion
167
References
168
8
TLU
Prevention in Power-Rail
ESD
Clamp Circuits
169
8.1
In
LV
CMOS ICs
169
8.1.1
Power-Rail
ESD
Clamp Circuits
171
8.1.2
TLU-Like Issues in
LV
Power-Rail
ESD
Clamp Circuits
174
8.1.3
Design of TLU-Free Power-Rail
ESD
Clamp Circuits
183
8.2
In HV CMOS ICs
189
8.2.1
High-Voltage
ESD
Protection Devices
190
8.2.2
Design of TLU-Free Power-Rail
ESD
Clamp Circuits
197
8.3
Conclusion
204
References
205
9
Summary
207
9.1
TLU
in CMOS ICs
207
9.2
Extraction of Compact and Safe Layout Rules for Latchup
Prevention
209
Appendix A: Practical Application
—
Extractions of Latchup Design
Rules in
a
0.18-μιη
1.8V/3.3V Suicided CMOS Process
211
АЛ
For I/O Cells
211
A.
1.1
Nomenclature
211
A.
1.2
I/O Cells with Double Guard Rings
212
A.
1.3
I/O Cells with a Single Guard Ring
215
A.
1.4
Suggested Layout Rules for I/O Cells
221
A.2 For Internal Circuits
223
A.2.1 Nomenclature
223
A.2.2 Design of Test Structures
223
A.2.3 Latchup Immunity Dependency of Internal Circuits
224
A.2.4 Suggested Layout Rules for Internal Circuits
226
A.3 For between I/O and Internal Circuits
226
A.3.1 Nomenclature
226
A.3.2 I/O and Internal Circuits (SCR)
227
Contents ix
A.3.3 I/O
and the Internal Circuits (Ring Oscillator)
233
A.3.4 Suggested Layout Rules for between I/O and the
Internal Circuits
235
A.4 For Circuits across Two Different Power Domains
237
A.4.1 Nomenclature
237
A.4.2 Design of Test Structures
237
A.4.3 Latchup Immunity Dependency between Two Different
Power Domains
241
A.4.4 Suggested Layout Rules between Two Different Power
Domains
242
A.5 Suggested Layout Guidelines
244
A.5.1 Latchup Design Guidelines for I/O Circuits
244
A.5.2 Latchup Design Guidelines for between I/O and the
Internal Circuits
245
A.5.3 Latchup Design Guidelines for Internal Circuits
246
A.5.
4
Latchup Design Guidelines for Circuits across Two
Different Power Domains
246
Index
247
|
| any_adam_object | 1 |
| author | Ker, Ming-Dou Hsu, Sheng-Fu |
| author_facet | Ker, Ming-Dou Hsu, Sheng-Fu |
| author_role | aut aut |
| author_sort | Ker, Ming-Dou |
| author_variant | m d k mdk s f h sfh |
| building | Verbundindex |
| bvnumber | BV035497276 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| ctrlnum | (OCoLC)264669592 (DE-599)BVBBV035497276 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02549nam a2200409zc 4500</leader><controlfield tag="001">BV035497276</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20091110 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">090519s2009 si ad|| |||| 00||| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2008045600</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470824078</subfield><subfield code="c">cloth</subfield><subfield code="9">978-0-470-82407-8</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)264669592</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV035497276</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">si</subfield><subfield code="c">SG</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-703</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7871.99.M44</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4960</subfield><subfield code="0">(DE-625)157426:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ker, Ming-Dou</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Transient-induced latchup in CMOS integrated circuits</subfield><subfield code="c">Ming-Dou Ker and Sheng-Fu Hsu</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Transient induced latchup in CMOS integrated circuits</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Singapore</subfield><subfield code="b">Wiley [u.a.]</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIII, 249 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Erscheint: Mai 2009</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process." -- Publisher's description.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary</subfield><subfield code="x">Defects</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary</subfield><subfield code="x">Reliability</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hsu, Sheng-Fu</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung UB Bayreuth</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017553565&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017553565</subfield></datafield></record></collection> |
| id | DE-604.BV035497276 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:38:56Z |
| institution | BVB |
| isbn | 9780470824078 |
| language | English |
| lccn | 2008045600 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017553565 |
| oclc_num | 264669592 |
| open_access_boolean | |
| owner | DE-703 |
| owner_facet | DE-703 |
| physical | XIII, 249 S. Ill., graph. Darst. |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Wiley [u.a.] |
| record_format | marc |
| spelling | Ker, Ming-Dou Verfasser aut Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu Transient induced latchup in CMOS integrated circuits Singapore Wiley [u.a.] 2009 XIII, 249 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Erscheint: Mai 2009 "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process." -- Publisher's description. Metal oxide semiconductors, Complementary Defects Metal oxide semiconductors, Complementary Reliability Hsu, Sheng-Fu Verfasser aut Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017553565&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Ker, Ming-Dou Hsu, Sheng-Fu Transient-induced latchup in CMOS integrated circuits Metal oxide semiconductors, Complementary Defects Metal oxide semiconductors, Complementary Reliability |
| title | Transient-induced latchup in CMOS integrated circuits |
| title_alt | Transient induced latchup in CMOS integrated circuits |
| title_auth | Transient-induced latchup in CMOS integrated circuits |
| title_exact_search | Transient-induced latchup in CMOS integrated circuits |
| title_full | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_fullStr | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_full_unstemmed | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_short | Transient-induced latchup in CMOS integrated circuits |
| title_sort | transient induced latchup in cmos integrated circuits |
| topic | Metal oxide semiconductors, Complementary Defects Metal oxide semiconductors, Complementary Reliability |
| topic_facet | Metal oxide semiconductors, Complementary Defects Metal oxide semiconductors, Complementary Reliability |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017553565&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT kermingdou transientinducedlatchupincmosintegratedcircuits AT hsushengfu transientinducedlatchupincmosintegratedcircuits |