Shared resources for multiple instruction stream pipelined processors:
This research has centered on the performance of functional resources that are used by a single multiple-stream pipelined processor. Such resources include arithmetic functional units and the modules that compose an interleaved memory. The functional requirements of such resources is that they perfo...
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| Main Author: | |
|---|---|
| Format: | Thesis Microfilm Book |
| Language: | English |
| Published: |
1979
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| Edition: | [Mikrofiche-Ausg.] |
| Subjects: | |
| Summary: | This research has centered on the performance of functional resources that are used by a single multiple-stream pipelined processor. Such resources include arithmetic functional units and the modules that compose an interleaved memory. The functional requirements of such resources is that they perform some operation and resynchronize their results with the associated stream in the pipelined processor. In some instances, a replicated or pipelined resource can be used to achieve the required performance. However, in this research a simple non-pipelined unit with a fixed cycle time is investigated as a lower cost alternative. This resource is characterized by a cycle time, c, and a deadline, d, which if missed results in a penalty of one non-compute pass through the pipeline. The performance of this type of resource for various resource scheduling techniques has been determined through the use of Markov modeling and some model reduction methods. It is shown that very high performance can be obtained when effective use is made of the available deadlines. An extension to this model allows the consideration of resources with access times not equal to their cycle times. Various applications for this type of resource are examined including an implementation of a cost-effective control store which attains high performance through the use of interleaving |
| Physical Description: | IV, 173 S. graph. Darst. |
Staff View
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| 520 | |a This research has centered on the performance of functional resources that are used by a single multiple-stream pipelined processor. Such resources include arithmetic functional units and the modules that compose an interleaved memory. The functional requirements of such resources is that they perform some operation and resynchronize their results with the associated stream in the pipelined processor. In some instances, a replicated or pipelined resource can be used to achieve the required performance. However, in this research a simple non-pipelined unit with a fixed cycle time is investigated as a lower cost alternative. This resource is characterized by a cycle time, c, and a deadline, d, which if missed results in a penalty of one non-compute pass through the pipeline. The performance of this type of resource for various resource scheduling techniques has been determined through the use of Markov modeling and some model reduction methods. It is shown that very high performance can be obtained when effective use is made of the available deadlines. An extension to this model allows the consideration of resources with access times not equal to their cycle times. Various applications for this type of resource are examined including an implementation of a cost-effective control store which attains high performance through the use of interleaving | ||
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| genre_facet | Hochschulschrift |
| id | DE-604.BV035426527 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:34:59Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017346980 |
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| physical | IV, 173 S. graph. Darst. |
| publishDate | 1979 |
| publishDateSearch | 1979 |
| publishDateSort | 1979 |
| record_format | marc |
| spelling | Emer, Joel Springer Verfasser aut Shared resources for multiple instruction stream pipelined processors Joel Springer Emer [Mikrofiche-Ausg.] 1979 IV, 173 S. graph. Darst. txt rdacontent h rdamedia he rdacarrier Urbana, Ill., Univ., Diss., 1979 This research has centered on the performance of functional resources that are used by a single multiple-stream pipelined processor. Such resources include arithmetic functional units and the modules that compose an interleaved memory. The functional requirements of such resources is that they perform some operation and resynchronize their results with the associated stream in the pipelined processor. In some instances, a replicated or pipelined resource can be used to achieve the required performance. However, in this research a simple non-pipelined unit with a fixed cycle time is investigated as a lower cost alternative. This resource is characterized by a cycle time, c, and a deadline, d, which if missed results in a penalty of one non-compute pass through the pipeline. The performance of this type of resource for various resource scheduling techniques has been determined through the use of Markov modeling and some model reduction methods. It is shown that very high performance can be obtained when effective use is made of the available deadlines. An extension to this model allows the consideration of resources with access times not equal to their cycle times. Various applications for this type of resource are examined including an implementation of a cost-effective control store which attains high performance through the use of interleaving Mikroform-Ausgabe Ann Arbor, Mich. Univ. Microfilms Internat. 1980 2 Mikrofiches Mikrofiche-Ausg.: s1980 Operations Research scgdst Computer Hardware scgdst Processing equipment dtict Multiprocessors dtict Network flows dtict Performance(engineering) dtict Theses dtict Memory devices dtict Scheduling dtict Access time dtict Computer aided instruction dtict Markov processes dtict Electrical engineering dtict Access time / dtict Computer Hardware / scgdst Computer aided instruction / dtict Electrical engineering / dtict Markov processes / dtict Memory devices / dtict Multiprocessors / dtict Network flows / dtict Operations Research / scgdst Performance(engineering) / dtict Processing equipment / dtict Scheduling / dtict Theses / dtict (DE-588)4113937-9 Hochschulschrift gnd-content Reproduktion von Emer, Joel Springer Shared resources for multiple instruction stream pipelined processors 1979 |
| spellingShingle | Emer, Joel Springer Shared resources for multiple instruction stream pipelined processors Operations Research scgdst Computer Hardware scgdst Processing equipment dtict Multiprocessors dtict Network flows dtict Performance(engineering) dtict Theses dtict Memory devices dtict Scheduling dtict Access time dtict Computer aided instruction dtict Markov processes dtict Electrical engineering dtict Access time / dtict Computer Hardware / scgdst Computer aided instruction / dtict Electrical engineering / dtict Markov processes / dtict Memory devices / dtict Multiprocessors / dtict Network flows / dtict Operations Research / scgdst Performance(engineering) / dtict Processing equipment / dtict Scheduling / dtict Theses / dtict |
| subject_GND | (DE-588)4113937-9 |
| title | Shared resources for multiple instruction stream pipelined processors |
| title_auth | Shared resources for multiple instruction stream pipelined processors |
| title_exact_search | Shared resources for multiple instruction stream pipelined processors |
| title_full | Shared resources for multiple instruction stream pipelined processors Joel Springer Emer |
| title_fullStr | Shared resources for multiple instruction stream pipelined processors Joel Springer Emer |
| title_full_unstemmed | Shared resources for multiple instruction stream pipelined processors Joel Springer Emer |
| title_short | Shared resources for multiple instruction stream pipelined processors |
| title_sort | shared resources for multiple instruction stream pipelined processors |
| topic | Operations Research scgdst Computer Hardware scgdst Processing equipment dtict Multiprocessors dtict Network flows dtict Performance(engineering) dtict Theses dtict Memory devices dtict Scheduling dtict Access time dtict Computer aided instruction dtict Markov processes dtict Electrical engineering dtict Access time / dtict Computer Hardware / scgdst Computer aided instruction / dtict Electrical engineering / dtict Markov processes / dtict Memory devices / dtict Multiprocessors / dtict Network flows / dtict Operations Research / scgdst Performance(engineering) / dtict Processing equipment / dtict Scheduling / dtict Theses / dtict |
| topic_facet | Operations Research Computer Hardware Processing equipment Multiprocessors Network flows Performance(engineering) Theses Memory devices Scheduling Access time Computer aided instruction Markov processes Electrical engineering Access time / dtict Computer Hardware / scgdst Computer aided instruction / dtict Electrical engineering / dtict Markov processes / dtict Memory devices / dtict Multiprocessors / dtict Network flows / dtict Operations Research / scgdst Performance(engineering) / dtict Processing equipment / dtict Scheduling / dtict Theses / dtict Hochschulschrift |
| work_keys_str_mv | AT emerjoelspringer sharedresourcesformultipleinstructionstreampipelinedprocessors |