Integrated circuit and system design: power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2009
|
| Schriftenreihe: | Lecture notes in computer science
5349 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Parallel als Online-Ausg. erschienen Parallel als Online-Ausg. erschienen |
| Beschreibung: | XIII, 462 S. Ill., graph. Darst. 235 mm x 155 mm |
| ISBN: | 3540959475 9783540959472 |
Internformat
MARC
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| 245 | 1 | 0 | |a Integrated circuit and system design |b power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers |c Lars Svensson ... (eds.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2009 | |
| 300 | |a XIII, 462 S. |b Ill., graph. Darst. |c 235 mm x 155 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 5349 | |
| 500 | |a Parallel als Online-Ausg. erschienen | ||
| 500 | |a Parallel als Online-Ausg. erschienen | ||
| 650 | 4 | |a Entwurfsautomation - Kongress - Lissabon <2008> | |
| 650 | 4 | |a Computer-aided design |v Congresses | |
| 650 | 4 | |a Computers |x Power supply |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Design and construction |v Congresses | |
| 650 | 4 | |a Integrated circuits |x Testing |v Congresses | |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
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| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-017172322 | |
Datensatz im Suchindex
| _version_ | 1820875109687099392 |
|---|---|
| adam_text |
TABLE OF CONTENTS
SESSION 1: LOW-LEAKAGE AN
D SUBTHRESHOL
D CIRCUIT
S
SUBTHRESHOLD FI
R FILTE
R ARCHITECTUR
E FOR ULTR
A LOW POWER
APPLICATIONS 1
BISWAJIT MISHRA AND BASHIR M. AL-HASHIMI
REVERSE VGS STATI
C CMOS (RVGS-SCMOS); A NEW TECHNIQUE FOR
DYNAMICALLY COMPENSATING TH
E PROCESS VARIATIONS IN SUB-THRESHOLD
DESIGNS 11
BAHMAN KHERADMAND BOROUJENI, CHRISTIAN PIGUET, AND
YUSUF LEBLEBICI
IMPROVING TH
E POWER-DELAY PERFORMANCE IN SUBTHRESHOLD
SOURCE-COUPLED LOGIC CIRCUITS 21
ANNIN TAJALLI, MASSIMO ALIOTO, ELIZABETH J. BRAUER, AND
YUSUF LEBLEBICI
DESIGN AN
D EVALUATION OF MIXED 3T-4
T FINFE
T STACKS FOR LEAKAGE
REDUCTION 31
MATTEO AGOSTINELLI, MASSIMO ALIOTO, DAVID ESSENI, AND LUCA SELMI
SESSION 2: LOW-POWER METHOD
S AN
D MODEL
S
TEMPORAL DISCHARGE CURREN
T DRIVEN CLUSTERING FOR IMPROVED LEAKAGE
POWER REDUCTION IN ROW-BASED POWER-GATING 42
ASHOKA SATHANUR, LUCA BENINI, ALBERTO MACII, ENRICO MACII, AND
MASSIMO PONCINO
INTELLIGATE: SCALABLE DYNAMIC INVARIANT LEARNING FOR POWER
REDUCTION 52
RONI WIENER, GILA KAMHI, AND MOSHE Y. VARDI
ANALYSIS OF EFFECTS OF INPU
T ARRIVAL TIME VARIATIONS ON ON-CHIP BUS
POWER CONSUMPTION 62
MASANORI MUROYAMA, TOHRU ISHIHARA, AND HIROTO YASUURA
POWER-AWAR
E DESIG
N VI
A MICRO-ARCHITECTURA
L LIN
K T
O IMPLEMENTATIO
N .
. 7
2
YONI AIZIK, GILA KAMHI, YAEL ZBAR, HADAS RONEN, AND
MUHAMMAD ABOZAED
UNTRADITIONA
L APPROACH T
O COMPUTE
R ENERGY REDUCTION 82
VASILY G. MOSHNYAGA
BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/992291658
DIGITALISIERT DURCH
X TABLE OF CONTENTS
SESSION 3: ARITHMETIC AND MEMORIES
MIXED RADIX-
2 AN
D HIGH-RADIX RNS BASES FOR LOW-POWER
MULTIPLICATIO
N 93
IOANNIS KOURETAS AND VASSILIS PALIOURAS
POWER OPTIMIZATIO
N OF PARALLE
L MULTIPLIERS IN SYSTEMS WIT
H VARIABLE
WORD-LENGT
H 103
SAEEID TAHMASBI OSKUII, PER GUNNAR KJELDSBERG,
LARS LUNDHEIM, AND ASGHAR HAVASHKI
A DESIGN SPACE COMPARISON OF 6T AN
D 8T SRAM CORE-CELLS 116
FLORIAN BAUER, GEORG GEORGAKOS, AND DORIS SCHMITT-LANDSIEDEL
LATCHE
D CMOS DRAM SENSE AMPLIFIER YIELD ANALYSIS AN
D
OPTIMIZATIO
N 126
YAN LI, HELMUT SCHNEIDER, FLORIAN SCHNABEL, ROLAND THEWES, AND
DORIS SCHMITT-LANDSIEDEL
SESSION 4: VARIABILITY AND STATISTICAL TIMING
UNDERSTANDIN
G TH
E EFFECT OF INTRADI
E RANDO
M PROCESS VARIATION
S IN
NANOMETE
R DOMINO LOGIC 136
MASSIMO ALIOTO, GAETANO PALUMBO, AND MELITA PENNISI
A STUD
Y ON CMOS TIM
E UNCERTAINT
Y WIT
H TECHNOLOGY SCALING 146
MONICA FIGUEIREDO AND RUI L. AGUIAR
STATI
C TIMIN
G MODEL EXTRACTIO
N FOR COMBINATIONA
L CIRCUIT
S 156
BING LI, CHRISTOPH KNOTH, WALTER SCHNEIDER, MANUEL SCHMIDT, AND
ULF SCHLICHTMANN
A NEW BOUNDIN
G TECHNIQUE FOR HANDLING ARBITRAR
Y CORRELATION
S IN
PATH-BASE
D SSTA 167
WALTER SCHNEIDER, MANUEL SCHMIDT, BING LI, AND ULF SCHLICHTMANN
STATISTICA
L MODELING AN
D ANALYSIS OF STATI
C LEAKAGE AN
D DYNAMIC
SWITCHING POWER 178
HOWARD CHEN, SCOTT NEELY, JINJUN XIONG, VLADIMIR ZOLOTOV, AND
CHANDU VISWESWARIAH
SESSION 5: SYNCHRONIZATION AND INTERCONNECT
LOGIC SYNTHESIS OF HANDSHAK
E COMPONENT
S USING STRUCTURA
L CLUSTERIN
G
TECHNIQUES 188
FRANCISCO FERNAENDEZ-NOGUEIRA AND JOSEP CARMONA
FAST UNIVERSAL SYNCHRONIZERS 199
ROSTISLAV (REUVEN) DOBKIN AND RAN GINOSAR
TABLE OF CONTENTS XI
A PERFORMANCE-DRIVEN MULTILEVEL FRAMEWORK FOR TH
E X-BASED FULL-CHIP
ROUTE
R 209
TSUNG- YI HO
PMD
: A LOW-POWER CODE FOR NETWORKS-ON-CHIP BASED ON VIRTUA
L
CHANNELS 219
ALBERTO GARCIA-ORTIZ, LEANDRO S. INDRUSIAK, TUDOR MURGAN, AND
MANFRED GLESNER
SESSION 6: POWE
R SUPPLIE
S AN
D SWITCHIN
G NOIS
E
NEAR-FIELD MAPPING SYSTEM T
O SCAN IN TIME DOMAIN TH
E MAGNETIC
EMISSIONS OF INTEGRATE
D CIRCUITS 229
THOMAS ORDAS, MATHIEU LISART, ETIENNE SICARD,
PHILIPPE MAURINE, AND LIONEL TORRES
A COMPARISON BETWEEN TWO LOGIC SYNTHESIS FORMS FROM DIGITAL
SWITCHING NOISE VIEWPOINT 237
GIORGIO BOSELLI, VALENTINA CIRIANI, VALENTINO LIBERALI, AND
GABRIELLA TRUCCO
GENERATING WORST-CASE STIMULI FOR ACCURATE POWER GRID ANALYSIS 247
PEDRO MARQUES MORGADO, PAULO F. FLORES, JOSE C MONTEIRO, AND
L. MIGUEL SUEVEIRA
MONOLITHIC MULTI-MODE DC-DC CONVERTER WITH GAT
E VOLTAGE
OPTIMIZATIO
N 258
NUNO DIAS, MARCELINO SANTOS, FLORIBERTO LIMA, BEATRIZ BORGES, AND
JUELIO PAISANA
SESSION 7: LOW-POWER CIRCUITS
; RECONFIGURABL
E
ARCHITECTURE
S
ENERGY EFFICIENCY OF POWER-GATING IN LOW-POWER CLOCKED STORAGE
ELEMENTS 268
CHRISTOPHE GIACOMOTTO, MANDEEP SINGH, MILENA VRATONJIC, AND
VOJIN G. OKLOBDZIJA
A NEW DYNAMIC LOGIC CIRCUIT DESIGN FOR A
N EFFECTIVE TRADE-OFF
BETWEEN NOISE-IMMUNITY, PERFORMANCE AN
D ENERGY DISSIPATION 277
FABIO FRUSTACI, PASQUALE CORSONELLO, STEFANIA PERRI, AND
GIUSEPPE COCORULLO
ENERGY EFFICIENT ELLIPTIC CURVE PROCESSOR 287
MAURICE KELLER AND WILLIAM MARNANE
XII TABLE OF CONTENTS
ENERG
Y EFFICIENT COARSE-GRAI
N RECONFIGURABLE ARRA
Y FOR ACCELERATING
DIGITA
L SIGNAL PROCESSIN
G 297
MARCO LANUZZA, STEFANIA PERRI, PASQUALE CORSONELLO, AND
MARTIN MARGALA
POWER-EFHCIENT RECONFIGURATION CONTRO
L IN COARSE-GRAINED DYNAMICALLY
RECONFIGURABLE ARCHITECTURE
S 307
DMITRIJ KISSLER, ANDREAS STRAWETZ, FRANK HANNIG, AND JUERGEN TEICH
POSTE
R SESSION 1: CIRCUIT
S AN
D METHOD
S
SETTLING-OPTIMIZATION-BASE
D DESIGN APPROACH FOR THREE-STAG
E
NESTED-MILLER AMPLIFIERS 318
ANDREA PUGLIESE, FRANCESCO A. AMOROSO, GREGORIO CAPPUCCINO, AND
GIUSEPPE COCORULLO
ULTR
A LOW VOLTAGE HIGH SPEED DIFFERENTIAL CMOS INVERTER 328
OMID MIRMOTAHARI AND YNGVAR BERG
DIFFERENTIAL CAPACITANC
E ANALYSIS 338
MARCO BUCCI, RAIMONDO LUZZI, GIUSEPPE SCOTTI,
ANDREA SIMONETTI, AND ALESSANDRO TRIFILETTI
AUTOMATE
D SYNCHRONOUS-TO-ASYNCHRONOUS CIRCUIT
S CONVERSION:
A SURVEY 348
MARTIN SIMLASTIK AND VIERA STOPJAKOVA
NOVEL CROSS-TRANSITION ELIMINATIO
N TECHNIQUE IMPROVING DELAY AN
D
POWER CONSUMPTIO
N FOR ON-CHI
P BUSES 359
ANTOINE COURTAY, JOHANN LAURENT, OLIVIER SENTIEYS, AND
NATHALIE JULIEN
POSTE
R SESSION 2: POWE
R AN
D DELA
Y MODELIN
G
ANALYTICA
L HIGH-LEVEL POWER MODEL FOR LUT-BASE
D COMPONENT
S 369
RUZICA JEVTIC AND CARLOS CAMERAS
A FORMA
L APPROAC
H FOR ESTIMATIN
G EMBEDDE
D SYSTEM EXECUTIO
N TIM
E
AN
D ENERG
Y CONSUMPTIO
N 379
GUSTAVO CALLOU, PAULO MACIEL, ERMESON CARNEIRO, BRUNO NOGUEIRA,
EDUARDO TAVARES, AND MEUSE OLIVEIRA JR.
POWER DISSIPATION ASSOCIATED T
O INTERNA
L EFFECT TRANSITION
S IN STATI
C
CMO
S GATE
S 389
ALEJANDRO MILLAN, JORGE JUAN, MANUEL J. BELLIDO, DAVID GUERRERO,
PAULINO RUIZ-DE-CLAVIJO, AND JULIAN VIEJO
TABLE OF CONTENTS XIII
DISJOINT REGION PARTITIONIN
G FOR PROBABILISTI
C SWITCHING ACTIVITY
ESTIMATIO
N A
T REGISTER TRANSFER LEVEL 399
FELIPE MACHADO, TERESA RIESGO, AND YAGO TORROJA
DAT
A DEPENDENCE OF DELAY DISTRIBUTIO
N FOR A PLANA
R BUS 409
FRANCESC MOLL, JOAN FIGUERAS, AND ANTONIO RUBIO
SPECIAL SESSION: POWER OPTIMIZATION
S ADDRESSIN
G
RECONFIGURABL
E ARCHITECTURE
S
TOWARDS NOVEL APPROACHES IN DESIGN AUTOMATIO
N FOR FPG
A POWER
OPTIMIZATIO
N 419
JUANJO NOGUERA, ROBERT ESSER, KATARINA PAULSSON,
MICHAEL HUEBNER, AND JUERGEN BECKER
SMART ENUMERATION
: A SYSTEMATIC APPROACH T
O EXHAUSTIV
E SEARCH 429
TIM TODMAN, HAOHUAN FU, BRITTLE TSOI, OSKAR MENCER, AND
WAYNE LUK
AN EFFICIENT APPROACH FOR MANAGING POWER CONSUMPTION HOTSPOT
S
DISTRIBUTIO
N ON 3D FPGA
S 439
KOSTAS SIOZIOS AND DIMITRIOS SOUDRIS
INTERCONNECT POWER ANALYSIS FOR A COARSE-GRAINED RECONFIGURABLE
ARRAY PROCESSOR 449
MLADEN BEREKOVIC, FRANK BOUWENS, TOM VANDER AA, AND
DIEDERIK VERKEST
KEYNOTE
S (ABSTRACTS
)
INTEGRATIO
N OF POWER MANAGEMENT UNITS ONT
O TH
E SOC 458
FLORIBERTO LIMA
MODEL T
O HARDWAR
E MATCHIN
G FOR N
M SCALE TECHNOLOGIES 459
SANI NASSIF
POWER AN
D PROFIT: ENGINEERING IN TH
E ENVELOPE 460
TED VUCUREVIC
AUTHOR INDEX
461 |
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| genre_facet | Konferenzschrift 2008 Lissabon |
| id | DE-604.BV035368390 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:10:24Z |
| institution | BVB |
| institution_GND | (DE-588)16000900-5 |
| isbn | 3540959475 9783540959472 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017172322 |
| oclc_num | 310400666 |
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| owner_facet | DE-91G DE-BY-TUM DE-706 DE-83 DE-11 |
| physical | XIII, 462 S. Ill., graph. Darst. 235 mm x 155 mm |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers Lars Svensson ... (eds.) Berlin [u.a.] Springer 2009 XIII, 462 S. Ill., graph. Darst. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 5349 Parallel als Online-Ausg. erschienen Entwurfsautomation - Kongress - Lissabon <2008> Computer-aided design Congresses Computers Power supply Congresses Integrated circuits Design and construction Congresses Integrated circuits Testing Congresses Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2008 Lissabon gnd-content Entwurfsautomation (DE-588)4312536-0 s DE-604 Svensson, Lars Sonstige oth PATMOS 18 2008 Lissabon Sonstige (DE-588)16000900-5 oth Lecture notes in computer science 5349 (DE-604)BV000000607 5349 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017172322&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers Lecture notes in computer science Entwurfsautomation - Kongress - Lissabon <2008> Computer-aided design Congresses Computers Power supply Congresses Integrated circuits Design and construction Congresses Integrated circuits Testing Congresses Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)1071861417 |
| title | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers |
| title_auth | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers |
| title_exact_search | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers |
| title_full | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers Lars Svensson ... (eds.) |
| title_fullStr | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers Lars Svensson ... (eds.) |
| title_full_unstemmed | Integrated circuit and system design power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers Lars Svensson ... (eds.) |
| title_short | Integrated circuit and system design |
| title_sort | integrated circuit and system design power and timing modeling optimization and simulation 18th international workshop patmos 2008 lisbon portugal september 10 12 2008 revised selected papers |
| title_sub | power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008 ; revised selected papers |
| topic | Entwurfsautomation - Kongress - Lissabon <2008> Computer-aided design Congresses Computers Power supply Congresses Integrated circuits Design and construction Congresses Integrated circuits Testing Congresses Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Entwurfsautomation - Kongress - Lissabon <2008> Computer-aided design Congresses Computers Power supply Congresses Integrated circuits Design and construction Congresses Integrated circuits Testing Congresses Entwurfsautomation Konferenzschrift 2008 Lissabon |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017172322&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
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