Verfügbarkeit: CMOS :: THWS Bibkatalog

CMOS: mixed-signal circuit design

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Bibliographische Detailangaben
1. Verfasser:	Baker, Russel Jacob 1964- (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Hoboken, NJ Wiley [u.a.] 2009
Ausgabe:	2. ed.
Schriftenreihe:	IEEE Press series on microelectronic systems [6]
Schlagworte:	Metal oxide semiconductors, Complementary Mixed signal circuits / Design Electronic circuit design Circuits à signaux mixtes - Conception et construction Circuits électroniques - Calcul MOS complémentaires Mixed signal circuits > Design CMOS Integrierte Schaltung Mixed-Signal-Schaltung
Online-Zugang:	Inhaltsverzeichnis Klappentext
Beschreibung:	Previous ed.: New York: Wiley, 2002
Beschreibung:	XVI, 329 S. graph. Darst.
ISBN:	9780470290262 0470290269

Internformat

MARC


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Datensatz im Suchindex

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adam_text	Contents Preface xv Chapter 1 Signals, Filters, and Tools 1 1.1 Sinusoidal Signals ............................................... 1 1.1.1 The Pendulum Analogy 1 Describing Amplitude in the x-y Plane 3 In-Phase and Quadrature Signals 4 1.1.2 The Complex (z-) Plane 6 1.2 Comb Filters .................................................... 8 1.2.1 The Digital Comb Filter 11 1.2.2 The Digital Differentiator 14 1.2.3 An Intuitive Discussion of the z-Plane 15 1.2.4 Comb Filters with Multiple Delay Elements 17 1.2.5 The Digital Integrator 19 The Delaying Integrator 20 An Important Note 21 1.3 Representing Signals ........................................... 21 1.3.1 Exponential Fourier Series 22 1.3.2 Fourier Transform 23 Dirac Delta Function (Unit Impulse Response) 23 VII viii Contents Chapter 2 Sampling and Aliasing 27 2.1 Sampling ....................................................... 28 2.1.1 Impulse Sampling 28 A Note Concerning the AAF and the RCF 30 Time Domain Description of Reconstruction 31 An Important Note 33 2.1.2 Decimation 33 2.1.3 The Sample-and-Hold (S/H) 35 S/H Spectral Response 35 The Reconstruction Filter (RCF) 39 Circuit Concerns for Implementing the S/H 39 An Example 40 2.1.4 The Track-and-Hold (T/H) 41 2.1.5 Interpolation 43 Zero Padding 44 Hold Register 46 Linear Interpolation 49 2.1.6 K-Path Sampling 50 Switched-Capacitor Circuits 51 Non-Overlapping Clock Generation 53 2.2 Circuits ......................................................... 54 2.2.1 Implementing the S/H 54 Finite Op-Amp Gain-Bandwidth Product 55 Autozeroing 57 Correlated Double Sampling (CDS) 59 Selecting Capacitor Sizes 61 2.2.2 The S/H with Gain 61 Implementing Subtraction in the S/H 63 A Single-Ended to Differential Output S/H 65 2.2.3 The Discrete Analog Integrator (DAI) 66 A Note Concerning Block Diagrams 68 Fully-Differential DAI 69 DAI Noise Performance 70 Chapter 3 Analog Filters 73 3.1 Integrator Building Blocks ....................................... 73 3.1.1 Lowpass Filters 73 3.1.2 Active-RC Integrators 75 Contents Effects of Finite Op-Amp Gain Bandwidth Product, fun 78 Active-RC SNR 82 3.1.3 MOSFET-C Integrators 83 Why Use an Active Circuit (an Op-Amp)? 85 3.1.4 gm-C (Transconductor-C) Integrators 86 Common-Mode Feedback Considerations 88 A High-Frequency Transconductor 89 3.1.5 Discrete-Time Integrators 90 An Important Note 94 Exact Frequency Response of an Ideal Discrete-Time 94 Filter 3.2 Filtering Topologies ............................................. 95 3.2.1 The Bilinear Transfer Function 95 Active-RC Implementation 97 Transconductor-C Implementation 97 Switched-Capacitor Implementation 98 3.2.2 The Biquadratic Transfer Function 99 Active-RC Implementation 101 Switched-Capacitor Implementation 106 High Q 107 Q Peaking and Instability 112 Transconductor-C Implementation 114 Chapter 4 Digital Filters 119 4.1 SPICE Models for DACs and ADCs ............................ 119 4.1.1 The Ideal DAC 119 SPICE Modeling the Ideal DAC 120 4.1.2 The Ideal ADC 121 4.1.3 Number Representation 123 Increasing Word Size (Extending the Sign-Bit) 124 Adding Numbers and Overflow 125 Subtracting Numbers in Two s Complement Format 126 4.2 Sine-Shaped Digital Filters ..................................... 126 4.2.1 The Counter 126 Aliasing 127 The Accumulate-and-Dump 129 4.2.2 Lowpass Sine Filters 129 Averaging without Decimation: A Review 132 Contents Cascading Sine Filters 132 Finite and Infinite Impulse Response Filters 133 4.2.3 Bandpass and Highpass Sine Filters 134 Canceling Zeroes to Create Highpass and Bandpass 134 Filters Frequency Sampling Filters 138 4.2.4 Interpolation using Sine Filters 139 Additional Control 142 Cascade of Integrators and Combs 142 4.2.5 Decimation using Sine Filters 143 4.3 Filtering Topologies ............................................ 145 4.3.1 FIR Filters 145 4.3.2 Stability and Overflow 146 Overflow 147 4.3.3 The Bilinear Transfer Function 148 The Canonic Form (or Standard Form) of a Digital 151 Filter General Canonic Form of a Recursive Filter 154 4.3.4 The Biquadratic Transfer Function 155 Comparing Biquads to Sine-Shaped Filters 157 A Comment Concerning Multiplications 158 Chapter 5 Data Converter SNR 163 5.1 Quantization Noise ............................................ 163 5.1.1 Viewing the Quantization Noise Spectrum Using 164 Simulations Bennett s Criteria 165 An Important Note 166 RMS Quantization Noise Voltage 166 Treating Quantization Noise as a Random Variable 168 5.1.2 Quantization Noise Voltage Spectral Density 169 Calculating Quantization Noise from a SPICE 171 Spectrum Power Spectral Density 172 5.2 Signal-to-Noise Ratio (SNR) ................................... 173 Effective Number of Bits 173 Coherent Sampling 175 Signal-to-Noise Plus Distortion Ratio 176 Spurious Free Dynamic Range 177 Contents Dynamic Range 177 Specifying SNR and SNDR 178 5.2.1 Clock Jitter 178 Using Oversampling to Reduce Sampling Clock Jitter 181 Stability Requirements A Practical Note 182 5.2.2 A Tool: The Spectral Density 182 The Spectral Density of Deterministic Signals: An 183 Overview The Spectral Density of Random Signals: An Overview 185 Specifying Phase Noise from Measured Data 189 5.3 Improving SNR using Averaging ............................... 190 An Important Note 191 5.3.1 Using Averaging to Improve SNR 192 Ideal Signal-to-Noise Ratio 194 5.3.2 Linearity Requirements 194 5.3.3 Adding a Noise Dither 195 5.3.4 Jitter 198 5.3.5 Anti-Aliasing Filter 198 5.4 Using Feedback to Improve SNR .............................. 199 Chapter 6 Data Converter Design Basics 203 The One-Bit ADC and DAC 204 6.1 Passive Noise-Shaping ........................................ 205 6.1.1 Signal-to-Noise Ratio 208 6.1.2 Decimating and Filtering the Modulator s Output 209 SNR Calculation using a Sine Filter 211 6.1.3 Offset, Matching, and Linearity 212 Resistor Mismatch 213 The Feedback DAC 213 DAC Offset 214 Linearity of the First-Order Modulator 214 Dead Zones 215 6.2 Improving SNR and Linearity .................................. 215 6.2.1 Second-Order Passive Noise-Shaping 216 6.2.2 Passive Noise-Shaping Using Switched-Capacitors 218 6.2.3 Increasing SNR using K-Paths 220 Revisiting Switched-Capacitor Implementations 224 xii Contents Effects of the Added Amplifier on Linearity 224 6.2.4 Improving Linearity Using an Active Circuit 225 Second-Order Noise-Shaping 227 Signal-to-Noise Ratio 229 Discussion 230 Chapter 7 Noise-Shaping Data Converters 233 7.1 First-Order Noise Shaping ..................................... 233 A Digital First-Order NS Demodulator 235 7.1.1 Modulation Noise in First-Order NS Modulators 236 7.1.2 RMS Quantization Noise in a First-Order Modulator 237 7.1.3 Decimating and Filtering the Output of a NS 239 Modulator 7.1.4 Pattern Noise from DC Inputs (Limit Cycle 241 Oscillations) 7.1.5 Integrator and Forward Modulator Gain 243 7.1.6 Comparator Gain, Offset, Noise, and Hysteresis 246 7.1.7 Op-Amp Gain (Integrator Leakage) 247 7.1.8 Op-Amp Settling Time 248 7.1.9 Op-Amp Offset 250 7.1.10 Op-Amp Input-Referred Noise 250 7.1.11 Practical Implementation of the First-Order NS 251 Modulator 7.2 Second-Order Noise-Shaping .................................. 253 7.2.1 Second-Order Modulator Topology 253 7.2.2 Integrator Gain 257 Implementing Feedback Gains in the DAI 260 Using Two Delaying Integrators to Implement the 263 Second-Order Modulator 7.2.3 Selecting Modulator (Integrator) Gains 264 7.3 Noise-Shaping Topologies ..................................... 264 7.3.1 Higher-Order Modulators 265 M th-Order Modulator Topology 265 7.3.2 Filtering the Output of an M th-Order NS Modulator 266 7.3.3 Implementing Higher-Order, Single-Stage 267 Modulators 7.3.4 Multi-Bit Modulators 269 Simulating a Multibit NS Modulator Using SPICE 269 7.3.5 Error Feedback 271 Contents xiii Implementation Concerns 274 7.3.6 Cascaded Modulators 275 Second-Order (1-1) Modulators 275 Third-Order (1-1-1) Modulators 277 Third-Order (2-1 ) Modulators 277 Implementing the Additional Summing Input 279 Chapter 8 Bandpass Data Converters 285 8.1 Continuous-Time Bandpass Noise-Shaping .................... 287 8.1.1 Passive-Component Bandpass Modulators 287 An Important Note 289 8.1.2 Active-Component Bandpass Modulators 289 Signal-to-Noise Ratio 290 8.1.3 Modulators for Conversion at Radio Frequencies 291 8.2 Switched-Capacitor Bandpass Noise-Shaping ................. 292 8.2.1 Switched-Capacitor Resonators 292 8.2.2 Second-Order Modulators 294 8.2.3 Fourth-Order Modulators 296 A Common Error 297 A Comment about 1/f Noise 297 8.2.4 Digital I/Q Extraction to Baseband 297 Chapter 9 A High-Speed Data Converter 301 9.1 The Topology ................................................. 301 9.1.1 Clock Signals 301 Path Settling Time 302 9.1.2 Implementation 303 9.1.3 Filtering 306 Examples 307 Direction 312 9.1.4 Discussion 312 9.1.5 Understanding the Clock Signals 315 9.2 Practical Implemenation ....................................... 316 9.2.1 Generating the Clock Signals 316 9.2.2 The Components 318 The Switched-Capacitors 318 The Amplifier 318 The Clocked Comparator 319 9.2.3 The ADC 320 Contents 9.3 Conclusion 322 Index 325 Get ud to speed on mixed-siqnal circuit desian (MSD) is currently performed in industry by а select few gurus. While MSD techniques can be found scattered throughout hard-to- digest technical papers, it is difficult for someone new to the topic to get up to speed on the subject without the guidance of a mentor and the right environment in which to gain the relevant experience. CMOS Mixed-Signal Circuit Design, Second Edition fills the gap in the technical literarna· by providing a tutorial presentation of MSD techniques and integrating homework problems, netlists, and simulation examples, all of which are available for download via the book s Web site at CMOSedu.com. Additional features of the Second Ediríon include: Coverage of noise-shaping «.lata converters (delta-sigma topologies) Practical discussion Ы digital filtering and its uses in transistor-level circuit designs Design of analog Hirers for both reconstruction and anti-aliasing Transistor- and system-level design techniques and theory Presentation oí a topology for high-speed data conversion in nanometer CMOS iplemented with practical examples and discussions, CMOS Mixed-Sig Circuit Design, Second Editton is an ideal textbook for graduate students in mixed-signal circuit design courses. It is also an equally valuable reference for professionals who want to improve their skills in this area. R. JACOB (JAKE) BAKER, PhD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds over 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books. For a detailed biography, please visit: http^/CMOSedu.com/jbaker/jbaker.htm.
adam_txt	Contents Preface xv Chapter 1 Signals, Filters, and Tools 1 1.1 Sinusoidal Signals . 1 1.1.1 The Pendulum Analogy 1 Describing Amplitude in the x-y Plane 3 In-Phase and Quadrature Signals 4 1.1.2 The Complex (z-) Plane 6 1.2 Comb Filters . 8 1.2.1 The Digital Comb Filter 11 1.2.2 The Digital Differentiator 14 1.2.3 An Intuitive Discussion of the z-Plane 15 1.2.4 Comb Filters with Multiple Delay Elements 17 1.2.5 The Digital Integrator 19 The Delaying Integrator 20 An Important Note 21 1.3 Representing Signals . 21 1.3.1 Exponential Fourier Series 22 1.3.2 Fourier Transform 23 Dirac Delta Function (Unit Impulse Response) 23 VII viii Contents Chapter 2 Sampling and Aliasing 27 2.1 Sampling . 28 2.1.1 Impulse Sampling 28 A Note Concerning the AAF and the RCF 30 Time Domain Description of Reconstruction 31 An Important Note 33 2.1.2 Decimation 33 2.1.3 The Sample-and-Hold (S/H) 35 S/H Spectral Response 35 The Reconstruction Filter (RCF) 39 Circuit Concerns for Implementing the S/H 39 An Example 40 2.1.4 The Track-and-Hold (T/H) 41 2.1.5 Interpolation 43 Zero Padding 44 Hold Register 46 Linear Interpolation 49 2.1.6 K-Path Sampling 50 Switched-Capacitor Circuits 51 Non-Overlapping Clock Generation 53 2.2 Circuits . 54 2.2.1 Implementing the S/H 54 Finite Op-Amp Gain-Bandwidth Product 55 Autozeroing 57 Correlated Double Sampling (CDS) 59 Selecting Capacitor Sizes 61 2.2.2 The S/H with Gain 61 Implementing Subtraction in the S/H 63 A Single-Ended to Differential Output S/H 65 2.2.3 The Discrete Analog Integrator (DAI) 66 A Note Concerning Block Diagrams 68 Fully-Differential DAI 69 DAI Noise Performance 70 Chapter 3 Analog Filters 73 3.1 Integrator Building Blocks . 73 3.1.1 Lowpass Filters 73 3.1.2 Active-RC Integrators 75 Contents Effects of Finite Op-Amp Gain Bandwidth Product, fun 78 Active-RC SNR 82 3.1.3 MOSFET-C Integrators 83 Why Use an Active Circuit (an Op-Amp)? 85 3.1.4 gm-C (Transconductor-C) Integrators 86 Common-Mode Feedback Considerations 88 A High-Frequency Transconductor 89 3.1.5 Discrete-Time Integrators 90 An Important Note 94 Exact Frequency Response of an Ideal Discrete-Time 94 Filter 3.2 Filtering Topologies . 95 3.2.1 The Bilinear Transfer Function 95 Active-RC Implementation 97 Transconductor-C Implementation 97 Switched-Capacitor Implementation 98 3.2.2 The Biquadratic Transfer Function 99 Active-RC Implementation 101 Switched-Capacitor Implementation 106 High Q 107 Q Peaking and Instability 112 Transconductor-C Implementation 114 Chapter 4 Digital Filters 119 4.1 SPICE Models for DACs and ADCs . 119 4.1.1 The Ideal DAC 119 SPICE Modeling the Ideal DAC 120 4.1.2 The Ideal ADC 121 4.1.3 Number Representation 123 Increasing Word Size (Extending the Sign-Bit) 124 Adding Numbers and Overflow 125 Subtracting Numbers in Two's Complement Format 126 4.2 Sine-Shaped Digital Filters . 126 4.2.1 The Counter 126 Aliasing 127 The Accumulate-and-Dump 129 4.2.2 Lowpass Sine Filters 129 Averaging without Decimation: A Review 132 Contents Cascading Sine Filters 132 Finite and Infinite Impulse Response Filters 133 4.2.3 Bandpass and Highpass Sine Filters 134 Canceling Zeroes to Create Highpass and Bandpass 134 Filters Frequency Sampling Filters 138 4.2.4 Interpolation using Sine Filters 139 Additional Control 142 Cascade of Integrators and Combs 142 4.2.5 Decimation using Sine Filters 143 4.3 Filtering Topologies . 145 4.3.1 FIR Filters 145 4.3.2 Stability and Overflow 146 Overflow 147 4.3.3 The Bilinear Transfer Function 148 The Canonic Form (or Standard Form) of a Digital 151 Filter General Canonic Form of a Recursive Filter 154 4.3.4 The Biquadratic Transfer Function 155 Comparing Biquads to Sine-Shaped Filters 157 A Comment Concerning Multiplications 158 Chapter 5 Data Converter SNR 163 5.1 Quantization Noise . 163 5.1.1 Viewing the Quantization Noise Spectrum Using 164 Simulations Bennett's Criteria 165 An Important Note 166 RMS Quantization Noise Voltage 166 Treating Quantization Noise as a Random Variable 168 5.1.2 Quantization Noise Voltage Spectral Density 169 Calculating Quantization Noise from a SPICE 171 Spectrum Power Spectral Density 172 5.2 Signal-to-Noise Ratio (SNR) . 173 Effective Number of Bits 173 Coherent Sampling 175 Signal-to-Noise Plus Distortion Ratio 176 Spurious Free Dynamic Range 177 Contents Dynamic Range 177 Specifying SNR and SNDR 178 5.2.1 Clock Jitter 178 Using Oversampling to Reduce Sampling Clock Jitter 181 Stability Requirements A Practical Note 182 5.2.2 A Tool: The Spectral Density 182 The Spectral Density of Deterministic Signals: An 183 Overview The Spectral Density of Random Signals: An Overview 185 Specifying Phase Noise from Measured Data 189 5.3 Improving SNR using Averaging . 190 An Important Note 191 5.3.1 Using Averaging to Improve SNR 192 Ideal Signal-to-Noise Ratio 194 5.3.2 Linearity Requirements 194 5.3.3 Adding a Noise Dither 195 5.3.4 Jitter 198 5.3.5 Anti-Aliasing Filter 198 5.4 Using Feedback to Improve SNR . 199 Chapter 6 Data Converter Design Basics 203 The One-Bit ADC and DAC 204 6.1 Passive Noise-Shaping . 205 6.1.1 Signal-to-Noise Ratio 208 6.1.2 Decimating and Filtering the Modulator's Output 209 SNR Calculation using a Sine Filter 211 6.1.3 Offset, Matching, and Linearity 212 Resistor Mismatch 213 The Feedback DAC 213 DAC Offset 214 Linearity of the First-Order Modulator 214 Dead Zones 215 6.2 Improving SNR and Linearity . 215 6.2.1 Second-Order Passive Noise-Shaping 216 6.2.2 Passive Noise-Shaping Using Switched-Capacitors 218 6.2.3 Increasing SNR using K-Paths 220 Revisiting Switched-Capacitor Implementations 224 xii Contents Effects of the Added Amplifier on Linearity 224 6.2.4 Improving Linearity Using an Active Circuit 225 Second-Order Noise-Shaping 227 Signal-to-Noise Ratio 229 Discussion 230 Chapter 7 Noise-Shaping Data Converters 233 7.1 First-Order Noise Shaping . 233 A Digital First-Order NS Demodulator 235 7.1.1 Modulation Noise in First-Order NS Modulators 236 7.1.2 RMS Quantization Noise in a First-Order Modulator 237 7.1.3 Decimating and Filtering the Output of a NS 239 Modulator 7.1.4 Pattern Noise from DC Inputs (Limit Cycle 241 Oscillations) 7.1.5 Integrator and Forward Modulator Gain 243 7.1.6 Comparator Gain, Offset, Noise, and Hysteresis 246 7.1.7 Op-Amp Gain (Integrator Leakage) 247 7.1.8 Op-Amp Settling Time 248 7.1.9 Op-Amp Offset 250 7.1.10 Op-Amp Input-Referred Noise 250 7.1.11 Practical Implementation of the First-Order NS 251 Modulator 7.2 Second-Order Noise-Shaping . 253 7.2.1 Second-Order Modulator Topology 253 7.2.2 Integrator Gain 257 Implementing Feedback Gains in the DAI 260 Using Two Delaying Integrators to Implement the 263 Second-Order Modulator 7.2.3 Selecting Modulator (Integrator) Gains 264 7.3 Noise-Shaping Topologies . 264 7.3.1 Higher-Order Modulators 265 M th-Order Modulator Topology 265 7.3.2 Filtering the Output of an M th-Order NS Modulator 266 7.3.3 Implementing Higher-Order, Single-Stage 267 Modulators 7.3.4 Multi-Bit Modulators 269 Simulating a Multibit NS Modulator Using SPICE 269 7.3.5 Error Feedback 271 Contents xiii Implementation Concerns 274 7.3.6 Cascaded Modulators 275 Second-Order (1-1) Modulators 275 Third-Order (1-1-1) Modulators 277 Third-Order (2-1 ) Modulators 277 Implementing the Additional Summing Input 279 Chapter 8 Bandpass Data Converters 285 8.1 Continuous-Time Bandpass Noise-Shaping . 287 8.1.1 Passive-Component Bandpass Modulators 287 An Important Note 289 8.1.2 Active-Component Bandpass Modulators 289 Signal-to-Noise Ratio 290 8.1.3 Modulators for Conversion at Radio Frequencies 291 8.2 Switched-Capacitor Bandpass Noise-Shaping . 292 8.2.1 Switched-Capacitor Resonators 292 8.2.2 Second-Order Modulators 294 8.2.3 Fourth-Order Modulators 296 A Common Error 297 A Comment about 1/f Noise 297 8.2.4 Digital I/Q Extraction to Baseband 297 Chapter 9 A High-Speed Data Converter 301 9.1 The Topology . 301 9.1.1 Clock Signals 301 Path Settling Time 302 9.1.2 Implementation 303 9.1.3 Filtering 306 Examples 307 Direction 312 9.1.4 Discussion 312 9.1.5 Understanding the Clock Signals 315 9.2 Practical Implemenation . 316 9.2.1 Generating the Clock Signals 316 9.2.2 The Components 318 The Switched-Capacitors 318 The Amplifier 318 The Clocked Comparator 319 9.2.3 The ADC 320 Contents 9.3 Conclusion 322 Index 325 Get ud to speed on mixed-siqnal circuit desian (MSD) is currently performed in industry by а select few "gurus." While MSD techniques can be found scattered throughout hard-to- digest technical papers, it is difficult for someone new to the topic to get up to speed on the subject without the guidance of a mentor and the right environment in which to gain the relevant experience. CMOS Mixed-Signal Circuit Design, Second Edition fills the gap in the technical literarna· by providing a tutorial presentation of MSD techniques and integrating homework problems, netlists, and simulation examples, all of which are available for download via the book's Web site at CMOSedu.com. Additional features of the Second Ediríon include: Coverage of noise-shaping «.lata converters (delta-sigma topologies) Practical discussion Ы digital filtering and its uses in transistor-level circuit designs Design of analog Hirers for both reconstruction and anti-aliasing Transistor- and system-level design techniques and theory Presentation oí a topology for high-speed data conversion in nanometer CMOS iplemented with practical examples and discussions, CMOS Mixed-Sig Circuit Design, Second Editton is an ideal textbook for graduate students in mixed-signal circuit design courses. It is also an equally valuable reference for professionals who want to improve their skills in this area. R. JACOB (JAKE) BAKER, PhD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds over 200 granted or pending patents in integrated circuit design. Jake is the author of several circuit design books. For a detailed biography, please visit: http^/CMOSedu.com/jbaker/jbaker.htm.
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id	DE-604.BV035140230
illustrated	Illustrated
index_date	2024-07-02T22:26:55Z
indexdate	2024-07-09T21:23:12Z
institution	BVB
isbn	9780470290262 0470290269
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-016807623
oclc_num	300964949
open_access_boolean
owner	DE-703 DE-634 DE-92
owner_facet	DE-703 DE-634 DE-92
physical	XVI, 329 S. graph. Darst.
publishDate	2009
publishDateSearch	2009
publishDateSort	2009
publisher	Wiley [u.a.]
record_format	marc
series	IEEE Press series on microelectronic systems
series2	IEEE Press series on microelectronic systems
spelling	Baker, Russel Jacob 1964- Verfasser (DE-588)138111715 aut CMOS mixed-signal circuit design R. Jacob Baker 2. ed. Hoboken, NJ Wiley [u.a.] 2009 XVI, 329 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier IEEE Press series on microelectronic systems [6] Previous ed.: New York: Wiley, 2002 Metal oxide semiconductors, Complementary Mixed signal circuits / Design Electronic circuit design Circuits à signaux mixtes - Conception et construction Circuits électroniques - Calcul MOS complémentaires Mixed signal circuits Design CMOS (DE-588)4010319-5 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Mixed-Signal-Schaltung (DE-588)4756481-7 gnd rswk-swf CMOS (DE-588)4010319-5 s Mixed-Signal-Schaltung (DE-588)4756481-7 s DE-604 Integrierte Schaltung (DE-588)4027242-4 s 1\p DE-604 IEEE Press series on microelectronic systems [6] (DE-604)BV040358802 6 Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016807623&sequence=000003&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016807623&sequence=000004&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA Klappentext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk
spellingShingle	Baker, Russel Jacob 1964- CMOS mixed-signal circuit design IEEE Press series on microelectronic systems Metal oxide semiconductors, Complementary Mixed signal circuits / Design Electronic circuit design Circuits à signaux mixtes - Conception et construction Circuits électroniques - Calcul MOS complémentaires Mixed signal circuits Design CMOS (DE-588)4010319-5 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd
subject_GND	(DE-588)4010319-5 (DE-588)4027242-4 (DE-588)4756481-7
title	CMOS mixed-signal circuit design
title_auth	CMOS mixed-signal circuit design
title_exact_search	CMOS mixed-signal circuit design
title_exact_search_txtP	CMOS mixed-signal circuit design
title_full	CMOS mixed-signal circuit design R. Jacob Baker
title_fullStr	CMOS mixed-signal circuit design R. Jacob Baker
title_full_unstemmed	CMOS mixed-signal circuit design R. Jacob Baker
title_short	CMOS
title_sort	cmos mixed signal circuit design
title_sub	mixed-signal circuit design
topic	Metal oxide semiconductors, Complementary Mixed signal circuits / Design Electronic circuit design Circuits à signaux mixtes - Conception et construction Circuits électroniques - Calcul MOS complémentaires Mixed signal circuits Design CMOS (DE-588)4010319-5 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd
topic_facet	Metal oxide semiconductors, Complementary Mixed signal circuits / Design Electronic circuit design Circuits à signaux mixtes - Conception et construction Circuits électroniques - Calcul MOS complémentaires Mixed signal circuits Design CMOS Integrierte Schaltung Mixed-Signal-Schaltung
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016807623&sequence=000003&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016807623&sequence=000004&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA
volume_link	(DE-604)BV040358802
work_keys_str_mv	AT bakerrusseljacob cmosmixedsignalcircuitdesign

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