Advanced automation in formal verification of processors:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Aachen
Shaker
2009
|
| Schriftenreihe: | Berichte aus der Informatik
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | III, 173 S. graph. Darst. |
| ISBN: | 9783832286194 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1804145437585702912 |
|---|---|
| adam_text | IMAGE 1
CONTENTS
1 INTRODUCTION 1
2 BACKGROUND 11
2.1 BINARY DECISION DIAGRAMS 11
2.2 DECISION PROCEDURES 13
2.2.1 BOOLEAN SATISFIABILITY 14
2.2.2 SATISFIABILITY MODULO THEORIES 15
2.2.3 QUANTIFIED BOOLEAN FORMULAE 16
2.3 BOUNDED MODEL CHECKING 16
2.3.1 SEMANTICS OF BOUNDED PSL 17
2.3.2 ENCODING AS A SAT PROBLEM 21
2.3.3 FC-INDUCTION 23
2.3.4 O-INDUCTION 24
2.3.5 INTERVAL PROPERTY CHECKING IN THE ONESPIN FLOW . . .. 25 2.4 THE
WOLFRAM FRAMEWORK 28
3 BOTTOM-UP - FORMALIZING THE SPECIFICATION 31
3.1 BOUNDED MODEL CHECKING 33
3.1.1 RISC CPU 33
3.1.2 BLOCK LEVEL 34
3.1.3 INSTRUCTION SET ARCHITECTURE LEVEL 38
3.1.4 SOFTWARE LEVEL 41
3.1.5 SUMMARY 44
3.2 COVERAGE ANALYSIS 45
3.2.1 RELATED WORK 45
3.2.2 IDEA 47
3.2.3 GENERATING THE COVERAGE PROPERTY 47
3.2.4 APPLICABILITY AND LIMITATIONS 51
3.2.5 RESULTS 52
3.2.6 SUMMARY 57
3.3 PROPERTY ANALYSIS 58
BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/998313092
DIGITALISIERT DURCH
IMAGE 2
3.3.1 RELATED WORK 59
3.3.2 IDEA 59
3.3.3 ALGORITHM 60
3.3.4 DISCUSSION 62
3.3.5 RESULTS 63
3.3.6 SUMMARY 64
3.4 INVERSE PROPERTY CHECKING 65
3.4.1 RELATED WORK 65
3.4.2 ALGORITHM 65
3.4.3 INTEGRATION WITH COVERAGE ANALYSIS 68
3.4.4 RESULTS 70
3.4.5 SUMMARY 71
3.5 DISCUSSION 73
4 TOP-DOWN - PROCESSOR VERIFICATION METHODOLOGY 75
4.1 PROCESSOR DESIGN AND VERIFICATION 77
4.1.1 AUTOMATED PIPELINE DESIGN 77
4.1.2 INCREMENTAL DESIGN AND VERIFICATION 78
4.1.3 PROCESSOR VERIFICATION 78
4.2 VERIFICATION OF PROCESSORS BASED ON ARCHITECTURAL MODELS . .. 81
4.2.1 CONTRIBUTION AND RELATED WORK 82
4.2.2 OVERVIEW 83
4.2.3 ARCHITECTURE DESCRIPTION 86
4.2.4 GENERAL PROCESSOR MODEL 88
4.2.5 GENERATING THE PROPERTY SUITE 100
4.2.6 COMPLETENESS 105
4.2.7 APPLICATIONS 106
4.2.8 APPLICABILITY AND LIMITATIONS 114
4.2.9 SUMMARY 115
4.3 GENERATING AN INSTRUCTION SET SIMULATOR 117
4.3.1 BACKGROUND AND RELATED WORK 119
4.3.2 GENERATION OF THE ISS 120
4.3.3 RESULTS 126
4.3.4 SUMMARY 128
4.4 AUTOMATED SOFTWARE SYNTHESIS WITH ARCHITECTURAL MODELS . . . 129
4.4.1 ARCHITECTURE AND SOFTWARE SPECIFICATION 130
4.4.2 QBF MODEL AND ALGORITHM 133
4.4.3 APPLICATIONS 135
4.4.4 SUMMARY 137
5 CONCLUSIONS AND PERSPECTIVES 139
IMAGE 3
A BOUNDED PSL SYNTAX 143
B ISA DESCRIPTION SYNTAX 149
GLOSSARY 157
BIBLIOGRAPHY 159
|
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| dewey-full | 004.22 004.16 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.22 004.16 |
| dewey-search | 004.22 004.16 |
| dewey-sort | 14.22 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| format | Thesis Book |
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| institution | BVB |
| isbn | 9783832286194 |
| language | English |
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| spelling | Kühne, Ulrich Verfasser aut Advanced automation in formal verification of processors Ulrich Kühne Aachen Shaker 2009 III, 173 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Berichte aus der Informatik Zugl.: Bremen, Univ., Diss., 2009 Verifikation (DE-588)4135577-5 gnd rswk-swf Formale Methode (DE-588)4333722-3 gnd rswk-swf Prozessor (DE-588)4176076-1 gnd rswk-swf Bounded Model Checking (DE-588)4769528-6 gnd rswk-swf Hardwareentwurf (DE-588)4159103-3 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Prozessor (DE-588)4176076-1 s Hardwareentwurf (DE-588)4159103-3 s Verifikation (DE-588)4135577-5 s Formale Methode (DE-588)4333722-3 s Bounded Model Checking (DE-588)4769528-6 s DE-188 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022342745&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Kühne, Ulrich Advanced automation in formal verification of processors Verifikation (DE-588)4135577-5 gnd Formale Methode (DE-588)4333722-3 gnd Prozessor (DE-588)4176076-1 gnd Bounded Model Checking (DE-588)4769528-6 gnd Hardwareentwurf (DE-588)4159103-3 gnd |
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| title | Advanced automation in formal verification of processors |
| title_auth | Advanced automation in formal verification of processors |
| title_exact_search | Advanced automation in formal verification of processors |
| title_full | Advanced automation in formal verification of processors Ulrich Kühne |
| title_fullStr | Advanced automation in formal verification of processors Ulrich Kühne |
| title_full_unstemmed | Advanced automation in formal verification of processors Ulrich Kühne |
| title_short | Advanced automation in formal verification of processors |
| title_sort | advanced automation in formal verification of processors |
| topic | Verifikation (DE-588)4135577-5 gnd Formale Methode (DE-588)4333722-3 gnd Prozessor (DE-588)4176076-1 gnd Bounded Model Checking (DE-588)4769528-6 gnd Hardwareentwurf (DE-588)4159103-3 gnd |
| topic_facet | Verifikation Formale Methode Prozessor Bounded Model Checking Hardwareentwurf Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022342745&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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