3-dimensional VLSI: a 2.5-dimensional integration scheme
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2010
|
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | XII, 190 S. graph. Darst. |
| ISBN: | 9783642041563 |
Internformat
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Datensatz im Suchindex
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CONTENTS LIST OF FIGURES AND TABLES IX 1 INTRODUCTION 1 1.1 2.5-D
INTEGRATION 5 1.2 ENABLING TECHNOLOGIES 8 1.2.1 FABRICATION TECHNOLOGY 8
1.2.2 TESTING METHODOLOGY AND FAULT TOLERANCE TECHNIQUE 9 1.2.3 DESIGN
TECHNOLOGY 10 1.3 OBJECTIVES AND BOOK ORGANIZATION 13 REFERENCES 16 2 A
COST COMPARISON OF VLSI INTEGRATION SCHEMES 21 2.1 NON-MONOLITHIC
INTEGRATION SCHEMES 22 2.1.1 MULTIPLE-RETICLE WAFER 23 2.1.2 MULTIPLE
CHIP MODULE (MCM) 23 2.1.3 THREE-DIMENSIONAL (3-D) INTEGRATION 24 2.2
YIELD ANALYSIS OF DIFFERENT VLSI INTEGRATION APPROACHES 26 2.2.1
MONOLITHIC SOC 28 2.2.2 MULTIPLE-RETICLE WAFER (MRW) 28 2.2.3
THREE-DIMENSIONAL (3-D) INTEGRATION 30 2.2.4 2.5-D SYSTEM INTEGRATION 31
2.2.5 MULTI-CHIP MODULE 34 V BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/1000032809 DIGITALISIERT DURCH VI 2.2.6 SUMMING UP 35
2.3 OBSERVATIONS 37 REFERENCES 38 3 DESIGN CASE STUDIES 42 3.1 CROSSBAR
43 3.2 A 2.5-D RAMBUS DRAM ARCHITECTURE 46 3.2.1 TACKLE THE LONG BUS
WIRE 46 3.2.2 SERIALIZED CHANNEL IN THE 3RD DIMENSION 48 3.3 A 2.5-D
REDESIGN OF PIPERENCH 50 3.3.1 THE 2.5-D IMPLEMENTATION 52 3.3.2
SIMULATION RESULTS 54 3.4 A 2.5-D INTEGRATED MICROPROCESSOR SYSTEM 56
3.4.1 A 2.5-D INTEGRATED MICROPROCESSOR SYSTEM 57 3.4.2 AN ANALYTICAL
PERFORMANCE MODEL 62 3.4.3 DETAILED PERFORMANCE SIMULATION FOR REDUCED
MEMORY LATENCY 66 3.5 OBSERVATIONS 69 REFERENCES 71 4 AN AUTOMATIC 2.5-D
LAYOUT DESIGN FLOW 74 4.1 A 2.5-D LAYOUT DESIGN FRAMEWORK 75 4.1.1 2.5-D
FLOORPLANNING 77 4.1.2 2.5-D PLACEMENT 78 4.1.3 2.5-D GLOBAL ROUTING 78
4.2 OBSERVATIONS 81 REFERENCES 81 VII 5 FLOORPLANNING FOR 2.5-D
INTEGRATION 83 5.1 FLOORPLAN LEVEL EVALUATION*CATEGORY 2 CIRCUITS 87
5.1.1 TECHNIQUE 87 5.1.2 RESULTS 89 5.2 FLOORPLAN LEVEL
EVALUATION*CATEGORY 3 CIRCUITS 91 5.2.1 TECHNIQUE 91 5.2.2 RESULTS 92
5.3 THERMAL DRIVEN FLOORPLANNING 93 5.3.1 CHIP LEVEL THERMAL MODELING
AND ANALYSIS FOR 2.5-D FLOORPLANNING 95 5.3.2 COUPLED TEMPERATURE AND
LEAKAGE ESTIMATION 99 5.3.3 2.5-D THERMAL DRIVEN FLOORPLANNING
TECHNIQUES 105 5.3.4 EXPERIMENTAL RESULTS 107 5.4 OBSERVATIONS 111
REFERENCES 1 13 6 PLACEMENT FOR 2.5-D INTEGRATION 117 6.1 PURE STANDARD
CELL DESIGNS 119 6.1.1 PLACEMENT TECHNIQUES 120 6.1.2 BENCHMARKS AND
LAYOUT MODEL 123 6.1.3 EVALUATION OF VERTICAL PARTITIONING STRATEGIES
125 6.1.4 WIRE LENGTH SCALING 126 6.1.5 WIRE LENGTH REDUCTION 129 6.1.6
WIRE LENGTH VS. INTER-CHIP CONTACT PITCH 133 6.2 MIXED MACRO AND
STANDARD CELL DESIGNS 134 6.2.1 PLACEMENT TECHNIQUES 136 6.2.2 RESULTS
AND ANALYSIS 138 VIII 6.3 OBSERVATIONS 140 REFERENCES 142 7 A ROAD MAP
OF 2.5-D INTEGRATION 144 7.1 STACKED MEMORY 145 7.2 DRAM INTEGRATION FOR
BANDWIDTH-DEMANDING APPLICATIONS 147 7.3 HYBRID SYSTEM INTEGRATION 151
7.4 EXTREMELY HIGH PERFORMANCE SYSTEMS 155 7.4.1 HIGHLY INTEGRATED IMAGE
SENSOR SYSTEM 155 7.4.2 RADAR-IN-CUBE 158 REFERENCES 160 8 CONCLUSION
AND FUTURE WORK 164 8.1 MAIN CONTRIBUTIONS AND CONCLUSIONS 165 8.2
FUTURE WORK 168 8.2.1 FABRICATION TECHNOLOGY FOR 2.5-D SYSTEMS 169 8.2.2
TESTING TECHNIQUES FOR 2.5-D INTEGRATION 171 8.2.3 DESIGN TECHNOLOGY FOR
2.5-D INTEGRATION 173 REFERENCES 186 INDEX 188 |
| any_adam_object | 1 |
| author | Deng, Yangdong Maly, Wojciech P. |
| author_facet | Deng, Yangdong Maly, Wojciech P. |
| author_role | aut aut |
| author_sort | Deng, Yangdong |
| author_variant | y d yd w p m wp wpm |
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| bvnumber | BV025599959 |
| classification_rvk | ZN 4952 |
| ctrlnum | (OCoLC)699658501 (DE-599)BVBBV025599959 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| indexdate | 2024-07-20T10:34:48Z |
| institution | BVB |
| isbn | 9783642041563 |
| language | English |
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| physical | XII, 190 S. graph. Darst. |
| publishDate | 2010 |
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| spelling | Deng, Yangdong Verfasser aut 3-dimensional VLSI a 2.5-dimensional integration scheme Yangdong Deng ; Wojciech P. Maly Three-dimensional VLSI Berlin [u.a.] Springer 2010 XII, 190 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Dreidimensionale Integration (DE-588)4218841-6 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Dreidimensionale Integration (DE-588)4218841-6 s Entwurfsautomation (DE-588)4312536-0 s DE-604 Maly, Wojciech P. Verfasser aut text/html http://deposit.dnb.de/cgi-bin/dokserv?id=3423678&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020195498&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Deng, Yangdong Maly, Wojciech P. 3-dimensional VLSI a 2.5-dimensional integration scheme Dreidimensionale Integration (DE-588)4218841-6 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4218841-6 (DE-588)4312536-0 (DE-588)4117388-0 |
| title | 3-dimensional VLSI a 2.5-dimensional integration scheme |
| title_alt | Three-dimensional VLSI |
| title_auth | 3-dimensional VLSI a 2.5-dimensional integration scheme |
| title_exact_search | 3-dimensional VLSI a 2.5-dimensional integration scheme |
| title_full | 3-dimensional VLSI a 2.5-dimensional integration scheme Yangdong Deng ; Wojciech P. Maly |
| title_fullStr | 3-dimensional VLSI a 2.5-dimensional integration scheme Yangdong Deng ; Wojciech P. Maly |
| title_full_unstemmed | 3-dimensional VLSI a 2.5-dimensional integration scheme Yangdong Deng ; Wojciech P. Maly |
| title_short | 3-dimensional VLSI |
| title_sort | 3 dimensional vlsi a 2 5 dimensional integration scheme |
| title_sub | a 2.5-dimensional integration scheme |
| topic | Dreidimensionale Integration (DE-588)4218841-6 gnd Entwurfsautomation (DE-588)4312536-0 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Dreidimensionale Integration Entwurfsautomation VLSI |
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