Holdings: Optimized ASIP synthesis from architecture description language models

Optimized ASIP synthesis from architecture description language models:

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Bibliographic Details
Main Authors:	Schliebusch, Oliver (Author), Meyr, Heinrich (Author), Leupers, Rainer (Author)
Format:	Thesis Book
Language:	English
Published:	Dordrecht Springer 2007
Subjects:	System-on-Chip Hardwarebeschreibungssprache Anwendungsspezifischer Prozessor Logiksynthese LISA > Programmiersprache Hochschulschrift
Online Access:	Inhaltstext Inhaltsverzeichnis
Physical Description:	XIV, 193 S. graph. Darst.
ISBN:	1402056850 9781402056857

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MARC


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adam_text	OPTIMIZED ASIP SYNTHESIS FROM ARCHITECTURE DESCRIPTION LANGUAGE MODELS VON DER FAKULTAT FUR ELEKTROTECHNIK UND INFORMATIONSTECHNIK DER RHEINISCH-WESTFALISCHEN TECHNISCHEN HOCHSCHULE AACHEN ZUR ERLANGUNG DES AKADEMISCHEN GRADES EINES DOKTORS DER INGENIEURWISSENSCHAFTEN GENEHMIGTE DISSERTATION VORGELEGT VON DIPLOM-INGENIEUR OLIVER SCHLIEBUSCH AUS BONN-BAD GODESBERG BERICHTER: UNIVERSITATSPROFESSOR DR. SC. TECHN. HEINRICH MEYR UNIVERSITATSPROFESSOR DR.-ING. TOBIAS G. NOLL TAG DER MUNDLICHEN PRIIFUNG: 21. APRIL 2006 D 82 (DISS.RWT H AACHEN) ULB DARMSTADT ILLLLLLLLLLLLLLLLLLLL 16605735 CONTENTS FOREWORD IX PREFACE XI 1. INTRODUCTION 1 1.1 FROM ASIC TO ASIP 1 1.2 HETEROGENEOUS ARCHITECTURES: COMPUTATIONAL PERFORMANCE VS. FLEXIBILITY 3 1.3 CHALLENGES OF ASIP DESIGN 5 1.4 ORGANIZATION OF THIS BOOK 8 2. ASIP DESIGN METHODOLOGIES 9 2.1 ADL BASED ASIP DESIGN 10 2.2 (RE)CONFIGURABLE ARCHITECTURES 13 2.3 HARDWARE DESCRIPTION LANGUAGES AND LOGIC REPRESENTATION 15 2.4 MOTIVATION OF THIS WORK 16 3. ASIP DESIGN BASED ON LISA 19 3.1 DESIGN SPACE EXPLORATION 19 3.2 SOFTWARE TOOLS GENERATION 20 3.3 SYSTEM SIMULATION AND INTEGRATION 23 4. A NEW ENTRY POINT FOR ASIP IMPLEMENTATION 25 4.1 ACCEPTANCE CRITERIA FOR AN AUTOMATIC ASIP IMPLEMENTATION 26 4.2 FROM ARCHITECTURE TO HARDWARE DESCRIPTION 27 5. LISA FRONTEND " 35 5.1 RESOURCE SECTION 36 5.2 LISA OPERATIONS 37 5.3 LISA OPERATION GRAPH 39 VI CONTENTS 5.4 REPRESENTING EXCLUSIVENESS IN CONFLICT AND COMPATIBILITY GRAPHS 48 5.5 EXCLUSIVENESS INFORMATION ON TH E LEVEL OF LISA OPERATIONS 50 5.6 EXCLUSIVENESS INFORMATION ON TH E BEHAVIORAL LEVEL 54 6. INTERMEDIATE REPRESENTATION 57 6.1 UNIFIED DESCRIPTION LAYER 57 6.2 OPTIMIZATION FRAMEWORK 63 6.3 VHDL, VERILOG AND SYSTEMC BACKEND 63 7. OPTIMIZATIONS BASED ON EXPLICIT ARCHITECTURAL INFORMATION 65 7.1 BASIC DFG BASED OPTIMIZATIONS 66 7.2 RESOURCE SHARING 71 7.3 DEPENDENCY MINIMIZATION 82 7.4 DECISION MINIMIZATION 84 8. CONFIGURABLE PROCESSOR FEATURES 87 8.1 PROCESSOR FEATURES 87 8.2 JTAG INTERFACE AND DEBUG MECHANISM GENERATION 88 8.3 ADAPTABILITY OF SYNTHESIS FRAMEWORK 98 9. CASE STUDY: AN ASIP FOR TURBO DECODING 101 9.1 TURBO DECODING BASED ON PROGRAMMABLE SOLUTIONS 101 9.2 THE TURBO DECODING PRINCIPLE 103 9.3 THE MAX-LOGMAP ALGORITHM 104 9.4 MEMORY ORGANIZATION AND ADDRESS GENERATION 106 9.5 INSTRUCTION-SET AND DATA-PAT H IMPLEMENTATION 109 9.6 INSTRUCTION SCHEDULE 110 9.7 PIPELINE.-STRUCTURE . 113 9.8 RESULTS 114 9.9 CONCLUDING REMARKS 115 10. CASE STUDIES: LEGACY CODE REUSE 117 10.1 LEVELS OF COMPATIBILITY 117 10.2 THE MOTOROLA 68HC11 ARCHITECTURE 118 10.3 THE INFINEON TECHNOLOGIES ASMD 125 CONTENTS VII 11. SUMMARY 131 APPENDICES 133 A CASE STUDIES 133 A.I ICORE 134 A.2 LT ARCHITECTURE FAMILY 136 B CFG AND DFG CONVERSIONS 141 B.I CFG T O DFG CONVERSION 141 B.2 DFG T O CFG CONVERSION 143 C DEBUG MECHANISM 145 C.I ADVANCED FEATURES OF DEBUG MECHANISMS 145 LIST OF FIGURES 149 LIST OF TABLES 153 REFERENCES 155 ABOUT TH E AUTHORS 164 INDEX 167
any_adam_object	1
author	Schliebusch, Oliver Meyr, Heinrich Leupers, Rainer
author_facet	Schliebusch, Oliver Meyr, Heinrich Leupers, Rainer
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discipline	Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
format	Thesis Book
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spelling	Schliebusch, Oliver Verfasser aut Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers Dordrecht Springer 2007 XIV, 193 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Zugl.: Aachen, Techn. Hochsch., Diss. System-on-Chip (DE-588)4740357-3 gnd rswk-swf Hardwarebeschreibungssprache (DE-588)4159102-1 gnd rswk-swf Anwendungsspezifischer Prozessor (DE-588)7582430-9 gnd rswk-swf Logiksynthese (DE-588)4348178-4 gnd rswk-swf LISA Programmiersprache (DE-588)4795068-7 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content System-on-Chip (DE-588)4740357-3 s Anwendungsspezifischer Prozessor (DE-588)7582430-9 s Logiksynthese (DE-588)4348178-4 s Hardwarebeschreibungssprache (DE-588)4159102-1 s LISA Programmiersprache (DE-588)4795068-7 s DE-604 Meyr, Heinrich Verfasser aut Leupers, Rainer Verfasser aut Erscheint auch als Online-Ausgabe 1-4020-5686-9 Erscheint auch als Online-Ausgabe 978-1-4020-5686-4 text/html http://deposit.dnb.de/cgi-bin/dokserv?id=2865908&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018592641&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Schliebusch, Oliver Meyr, Heinrich Leupers, Rainer Optimized ASIP synthesis from architecture description language models System-on-Chip (DE-588)4740357-3 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Anwendungsspezifischer Prozessor (DE-588)7582430-9 gnd Logiksynthese (DE-588)4348178-4 gnd LISA Programmiersprache (DE-588)4795068-7 gnd
subject_GND	(DE-588)4740357-3 (DE-588)4159102-1 (DE-588)7582430-9 (DE-588)4348178-4 (DE-588)4795068-7 (DE-588)4113937-9
title	Optimized ASIP synthesis from architecture description language models
title_auth	Optimized ASIP synthesis from architecture description language models
title_exact_search	Optimized ASIP synthesis from architecture description language models
title_full	Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers
title_fullStr	Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers
title_full_unstemmed	Optimized ASIP synthesis from architecture description language models by Oliver Schliebusch ; Heinrich Meyr and Rainer Leupers
title_short	Optimized ASIP synthesis from architecture description language models
title_sort	optimized asip synthesis from architecture description language models
topic	System-on-Chip (DE-588)4740357-3 gnd Hardwarebeschreibungssprache (DE-588)4159102-1 gnd Anwendungsspezifischer Prozessor (DE-588)7582430-9 gnd Logiksynthese (DE-588)4348178-4 gnd LISA Programmiersprache (DE-588)4795068-7 gnd
topic_facet	System-on-Chip Hardwarebeschreibungssprache Anwendungsspezifischer Prozessor Logiksynthese LISA Programmiersprache Hochschulschrift
url	http://deposit.dnb.de/cgi-bin/dokserv?id=2865908&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018592641&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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