APA-Zitierstil (7. Ausg.)

(2008). System Verilog for Verification: A Guide to Learning the Testbench Language Features. Springer Science+Business Media, LLC. https://doi.org/10.1007/978-0-387-76530-3

Chicago-Zitierstil (17. Ausg.)

System Verilog for Verification: A Guide to Learning the Testbench Language Features. Boston, MA: Springer Science+Business Media, LLC, 2008. https://doi.org/10.1007/978-0-387-76530-3.

MLA-Zitierstil (9. Ausg.)

System Verilog for Verification: A Guide to Learning the Testbench Language Features. Springer Science+Business Media, LLC, 2008. https://doi.org/10.1007/978-0-387-76530-3.