Application and standard driven LDPC code decoder development: = LDPC Code Decoder Entwicklung nach Applikationen und Standards
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
Kaiserslautern
Techn. Univ. Kaiserslautern
2008
|
| Edition: | Als Ms. gedr. |
| Series: | Forschungsberichte Mikroelektronik
11 |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis |
| Physical Description: | VI, 140 S. graph. Darst. |
| ISBN: | 9783939432722 |
Staff View
MARC
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| 246 | 1 | 1 | |a LDPC Code Decoder Entwicklung nach Applikationen und Standards |
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Record in the Search Index
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| adam_text | APPLICATION AND STANDARD DRIVEN LDPC CODE DECODER DEVELOPMENT LDPC CODE
DECODER ENTWICKLUNG NACH APPLIKATIONEN UND STANDARDS VOM FACHBEREICH
ELEKTROTECHNIK UND INFORMATIONSTECHNIK DER TECHNISCHEN UNIVERSITAT
KAISERSLAUTERN ZUR VERLEIHUNG DES AKADEMISCHEN GRADES DOKTOR DER
INGENIEURWISSENSCHAFTEN (DR.-ING.) EINGEREICHTE DISSERTATION DIPL.-INF.
TORBEN BRACK GEBOREN IN WERTHEIM AM MAIN TAG DER EINREICHUNG: 23. MAI
2007 TAG DER MIINDLICHEN PRIIFUNG: 17. APRIL 2008 DEKAN DES
FACHBEREICHS: PROF. DR.-ING. STEVEN LIU VORSITZENDER DER
PRIIFUNGSKOMMISSION: PROF. DR.-ING. RALPH URBANSKY 1. BERICHTERSTATTER:
PROF. DR.-ING. NORBERT WEHN 2. BERICHTERSTATTER: PROF. DR.-ING. LUCA
FANUCCI CONTENTS 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 A DECODER
DEVELOPMENT METHODOLOGY 2 1.2.1 CHOOSING THE ARCHITECTURE 3 1.2.2
EXPLOITING THE DESIGN SPACE 3 1.2.3 TAKING IMPLEMENTATION ISSUES INTO
ACCOUNT 5 1.3 CONTRIBUTIONS 5 1.4 OUTLINE 5 2 LDPC CODES AT A GLANCE 7
2.1 LDPC CODE ENCODING 8 2.2 IRREGULAR LDPC CODES 8 2.3 QUASI-CYCLIC
LDPC CODES 10 2.4 IRA CODES 11 2.5 LDPC CODE DECODING 12 2.5.1
SUBOPTIMAL DECODING 14 2.5.2 MODIFIED DECODING SCHEDULES 15 3 LDPC
DECODER ARCHITECTURE EVOLUTION 19 3.1 GENERIC ARCHITECTURE TEMPLATE 20
3.2 TWO-PHASE ARCHITECTURE 22 3.3 TWO-PHASE ARCHITECTURE WITH PN-BRANCH
24 3.4 SINGLE-PHASE ARCHITECTURE 25 3.5 LAYERED ARCHITECTURE 26 3.6
COMBINED ARCHITECTURE 28 IV CONTENTS 3.7 OTHER ARCHITECTURE CONCEPTS 29
3.7.1 FULLY FLEXIBLE ARCHITECTURES 29 3.7.2 PARTIAL LAYERED
ARCHITECTURES 29 3.7.3 STAGGERED DECODING ARCHITECTURES 30 3.8
ARCHITECTURE SELECTION 31 3.8.1 CONSIDERING THROUGHPUT AND LATENCY 31
3.8.2 CONSIDERING VLSI COMPLEXITY 35 3.8.3 CONSIDERING COMMUNICATIONS
PERFORMANCE 37 3.8.4 THE ARCHITECTURE PORTFOLIO 39 4 THE LDPC CODE
DECODER DESIGN SPACE 41 4.1 CODE GENERATION AND SELECTION 41 4.2
DECODING ALGORITHM COMPLEXITY 43 4.3 MAXIMUM NUMBER OF ITERATIONS 43 4.4
QUANTIZATION ISSUES 44 4.5 ARCHITECTURE PARALLELISM 45 4.6 TRAVELING THE
DESIGN SPACE 47 5 IMPLEMENTATION ISSUES 49 5.1 FLEXIBILITY ISSUES 50
5.1.1 IMPACT ON CHECK NODE IMPLEMENTATION 50 5.1.2 IMPACT ON NETWORK
IMPLEMENTATION 50 5.2 TECHNOLOGY ISSUES 52 5.2.1 FPGA IMPLEMENTATION 52
5.2.2 ASIC IMPLEMENTATION 52 5.3 POWER AND ENERGY ISSUES 53 5.3.1 EARLY
STOPPING CRITERIA 53 5.3.2 POWER PRE-SCHEDULING 56 5.4 MEMORY ISSUES 57
5.4.1 SINGLE PORT RAM PARTITIONING 57 5.4.2 COMPRESSED-CN STORAGE 60
CONTENTS V 6 STANDARD DRIVEN DESIGN STUDIES 63 6.1 DVB-S2 LDPC CODE . 63
6.2 WIMAX802.16E LDPC CODE 67 6.3 WIFI802.11N LDPC CODE 71 6.4 COMPARING
THE EXAMINED STANDARDS 73 7 APPLICATION DRIVEN DESIGN STUDIES 75 7.1 THE
4M0RE DEMONSTRATOR PROJECT 75 7.2 ULTRAWIDEBAND SYSTEM ENHANCEMENT 79
7.2.1 COMPLEMENTING THE CURRENT STANDARD 79 7.2.2 GOING BEYOND 1 GBPS 85
7.2.3 LDPC ENCODERS FOR THE UWB SYSTEM 85 7.3 THE SMALL ONE 89 7.4
CHALLENGING DUO-BINARY TURBO-CODES 91 8 CONCLUSIONS AND FUTURE WORK 97
8.1 CONCLUSIONS 97 8.2 FUTURE WORK 97 9 ZUSAMMENFASSUNG 99 9.1
MOTIVATION 99 9.2 EINE METHODIK ZUR DEKODERENTWICKLUNG 100 9.2.1
ARCHITEKTURAUSWAHL 100 9.2.2 ERGRIINDEN DES ENTWURFSRAUMES 101 9.2.3
EINBEZIEHUNG VON IMPLEMENTIERUNGSASPEKTEN 101 9.3 STANDARDBASIERTE
ENTWURFSSTUDIEN 102 9.4 ANWENDUNGSBASIERTE ENTWURFSSTUDIEN 103 9.5
EIGENE BEITRAGE 103 A CHANNEL CODING BASICS 107 A.I GENERAL
COMMUNICATION TERMS 107 A.2 CHANNEL CAPACITY 109 A.3 THE
MAXIMUM-A-POSTERIORI (MAP) ALGORITHM 110 A.4 THE MAP-ALGORITHM IN THE
LOGARITHMIC DOMAIN: LOG-MAP 112 VI CONTENTS B SYMBOLS 117 C
ABBREVIATIONS 121 BIBLIOGRAPHY 127 LIST OF FIGURES 135 LIST OF TABLES
139
|
| adam_txt |
APPLICATION AND STANDARD DRIVEN LDPC CODE DECODER DEVELOPMENT LDPC CODE
DECODER ENTWICKLUNG NACH APPLIKATIONEN UND STANDARDS VOM FACHBEREICH
ELEKTROTECHNIK UND INFORMATIONSTECHNIK DER TECHNISCHEN UNIVERSITAT
KAISERSLAUTERN ZUR VERLEIHUNG DES AKADEMISCHEN GRADES DOKTOR DER
INGENIEURWISSENSCHAFTEN (DR.-ING.) EINGEREICHTE DISSERTATION DIPL.-INF.
TORBEN BRACK GEBOREN IN WERTHEIM AM MAIN TAG DER EINREICHUNG: 23. MAI
2007 TAG DER MIINDLICHEN PRIIFUNG: 17. APRIL 2008 DEKAN DES
FACHBEREICHS: PROF. DR.-ING. STEVEN LIU VORSITZENDER DER
PRIIFUNGSKOMMISSION: PROF. DR.-ING. RALPH URBANSKY 1. BERICHTERSTATTER:
PROF. DR.-ING. NORBERT WEHN 2. BERICHTERSTATTER: PROF. DR.-ING. LUCA
FANUCCI CONTENTS 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 A DECODER
DEVELOPMENT METHODOLOGY 2 1.2.1 CHOOSING THE ARCHITECTURE 3 1.2.2
EXPLOITING THE DESIGN SPACE 3 1.2.3 TAKING IMPLEMENTATION ISSUES INTO
ACCOUNT 5 1.3 CONTRIBUTIONS 5 1.4 OUTLINE 5 2 LDPC CODES AT A GLANCE 7
2.1 LDPC CODE ENCODING 8 2.2 IRREGULAR LDPC CODES 8 2.3 QUASI-CYCLIC
LDPC CODES 10 2.4 IRA CODES 11 2.5 LDPC CODE DECODING 12 2.5.1
SUBOPTIMAL DECODING 14 2.5.2 MODIFIED DECODING SCHEDULES 15 3 LDPC
DECODER ARCHITECTURE EVOLUTION 19 3.1 GENERIC ARCHITECTURE TEMPLATE 20
3.2 TWO-PHASE ARCHITECTURE 22 3.3 TWO-PHASE ARCHITECTURE WITH PN-BRANCH
24 3.4 SINGLE-PHASE ARCHITECTURE 25 3.5 LAYERED ARCHITECTURE 26 3.6
COMBINED ARCHITECTURE 28 IV CONTENTS 3.7 OTHER ARCHITECTURE CONCEPTS 29
3.7.1 FULLY FLEXIBLE ARCHITECTURES 29 3.7.2 PARTIAL LAYERED
ARCHITECTURES 29 3.7.3 STAGGERED DECODING ARCHITECTURES 30 3.8
ARCHITECTURE SELECTION 31 3.8.1 CONSIDERING THROUGHPUT AND LATENCY 31
3.8.2 CONSIDERING VLSI COMPLEXITY 35 3.8.3 CONSIDERING COMMUNICATIONS
PERFORMANCE 37 3.8.4 THE ARCHITECTURE PORTFOLIO 39 4 THE LDPC CODE
DECODER DESIGN SPACE 41 4.1 CODE GENERATION AND SELECTION 41 4.2
DECODING ALGORITHM COMPLEXITY 43 4.3 MAXIMUM NUMBER OF ITERATIONS 43 4.4
QUANTIZATION ISSUES 44 4.5 ARCHITECTURE PARALLELISM 45 4.6 TRAVELING THE
DESIGN SPACE 47 5 IMPLEMENTATION ISSUES 49 5.1 FLEXIBILITY ISSUES 50
5.1.1 IMPACT ON CHECK NODE IMPLEMENTATION 50 5.1.2 IMPACT ON NETWORK
IMPLEMENTATION 50 5.2 TECHNOLOGY ISSUES 52 5.2.1 FPGA IMPLEMENTATION 52
5.2.2 ASIC IMPLEMENTATION 52 5.3 POWER AND ENERGY ISSUES 53 5.3.1 EARLY
STOPPING CRITERIA 53 5.3.2 POWER PRE-SCHEDULING 56 5.4 MEMORY ISSUES 57
5.4.1 SINGLE PORT RAM PARTITIONING 57 5.4.2 COMPRESSED-CN STORAGE 60
CONTENTS V 6 STANDARD DRIVEN DESIGN STUDIES 63 6.1 DVB-S2 LDPC CODE . 63
6.2 WIMAX802.16E LDPC CODE 67 6.3 WIFI802.11N LDPC CODE 71 6.4 COMPARING
THE EXAMINED STANDARDS 73 7 APPLICATION DRIVEN DESIGN STUDIES 75 7.1 THE
4M0RE DEMONSTRATOR PROJECT 75 7.2 ULTRAWIDEBAND SYSTEM ENHANCEMENT 79
7.2.1 COMPLEMENTING THE CURRENT STANDARD 79 7.2.2 GOING BEYOND 1 GBPS 85
7.2.3 LDPC ENCODERS FOR THE UWB SYSTEM 85 7.3 THE SMALL "ONE" 89 7.4
CHALLENGING DUO-BINARY TURBO-CODES 91 8 CONCLUSIONS AND FUTURE WORK 97
8.1 CONCLUSIONS 97 8.2 FUTURE WORK 97 9 ZUSAMMENFASSUNG 99 9.1
MOTIVATION 99 9.2 EINE METHODIK ZUR DEKODERENTWICKLUNG 100 9.2.1
ARCHITEKTURAUSWAHL 100 9.2.2 ERGRIINDEN DES ENTWURFSRAUMES 101 9.2.3
EINBEZIEHUNG VON IMPLEMENTIERUNGSASPEKTEN 101 9.3 STANDARDBASIERTE
ENTWURFSSTUDIEN 102 9.4 ANWENDUNGSBASIERTE ENTWURFSSTUDIEN 103 9.5
EIGENE BEITRAGE 103 A CHANNEL CODING BASICS 107 A.I GENERAL
COMMUNICATION TERMS 107 A.2 CHANNEL CAPACITY 109 A.3 THE
MAXIMUM-A-POSTERIORI (MAP) ALGORITHM 110 A.4 THE MAP-ALGORITHM IN THE
LOGARITHMIC DOMAIN: LOG-MAP 112 VI CONTENTS B SYMBOLS 117 C
ABBREVIATIONS 121 BIBLIOGRAPHY 127 LIST OF FIGURES 135 LIST OF TABLES
139 |
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| id | DE-604.BV023392665 |
| illustrated | Illustrated |
| index_date | 2024-07-02T21:20:35Z |
| indexdate | 2024-07-09T21:17:35Z |
| institution | BVB |
| isbn | 9783939432722 |
| language | English |
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| physical | VI, 140 S. graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
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| publisher | Techn. Univ. Kaiserslautern |
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| series | Forschungsberichte Mikroelektronik |
| series2 | Forschungsberichte Mikroelektronik |
| spelling | Brack, Torben 1979- Verfasser (DE-588)13575612X aut Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards Torben Brack LDPC Code Decoder Entwicklung nach Applikationen und Standards Als Ms. gedr. Kaiserslautern Techn. Univ. Kaiserslautern 2008 VI, 140 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Forschungsberichte Mikroelektronik 11 Zugl.: Kaiserslautern, Techn. Univ., Diss., 2008 Codierung (DE-588)4070059-8 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Codierung (DE-588)4070059-8 s DE-604 Forschungsberichte Mikroelektronik 11 (DE-604)BV012925671 11 HEBIS Datenaustausch Darmstadt application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016575581&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Brack, Torben 1979- Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards Forschungsberichte Mikroelektronik Codierung (DE-588)4070059-8 gnd |
| subject_GND | (DE-588)4070059-8 (DE-588)4113937-9 |
| title | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards |
| title_alt | LDPC Code Decoder Entwicklung nach Applikationen und Standards |
| title_auth | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards |
| title_exact_search | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards |
| title_exact_search_txtP | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards |
| title_full | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards Torben Brack |
| title_fullStr | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards Torben Brack |
| title_full_unstemmed | Application and standard driven LDPC code decoder development = LDPC Code Decoder Entwicklung nach Applikationen und Standards Torben Brack |
| title_short | Application and standard driven LDPC code decoder development |
| title_sort | application and standard driven ldpc code decoder development ldpc code decoder entwicklung nach applikationen und standards |
| title_sub | = LDPC Code Decoder Entwicklung nach Applikationen und Standards |
| topic | Codierung (DE-588)4070059-8 gnd |
| topic_facet | Codierung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016575581&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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